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Merge tag 'stm32-dt-for-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.4, round 1 Highlights: ---------- - MPU: - STM32MP13: - Add FMC support. - Add QSPI support. - Add 8 UART instances nodes. - Enable UART on STM32MP135F-DK: -UART1/UART8 used on expansion connector. -UART2 used for BT. -UART4 used for console. - STMP32MP15: - Add STM32MP151 support ( documentation + machine). - Uart fixes (slew rate, aliases clean-up). - Fix GPU YAMl issue. * tag 'stm32-dt-for-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: stm32: add initial documentation for STM32MP151 ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family ARM: dts: stm32: add FMC support on STM32MP13x SoC family ARM: dts: stm32: YAML validation fails for Argon Boards ARM: dts: stm32: YAML validation fails for Odyssey Boards ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl ARM: dts: stm32: add uart nodes on stm32mp13 ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx ARM: stm32: add support for STM32MP151 ARM: dts: stm32: fix spi1 pin assignment on stm32mp15 ARM: dts: stm32: drop invalid simple-panel compatible on stm32mp157c-lxa ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoM Link: https://lore.kernel.org/r/63987ed6-2813-15ff-e058-73312a730d61@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents d40a2f5 + 49f1d0b commit 83f91bb

16 files changed

Lines changed: 386 additions & 74 deletions

‎Documentation/arm/index.rst‎

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@@ -58,6 +58,7 @@ SoC-specific documents
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stm32/stm32f769-overview
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stm32/stm32f429-overview
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stm32/stm32mp13-overview
61+
stm32/stm32mp151-overview
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stm32/stm32mp157-overview
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stm32/stm32-dma-mdma-chaining
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‎Documentation/arm/stm32/stm32mp151-overview.rst‎

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===================
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STM32MP151 Overview
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===================
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Introduction
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------------
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8+
The STM32MP151 is a Cortex-A MPU aimed at various applications.
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It features:
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- Single Cortex-A7 application core
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- Standard memories interface support
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- Standard connectivity, widely inherited from the STM32 MCU family
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- Comprehensive security support
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More details:
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- Cortex-A7 core running up to @800MHz
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- FMC controller to connect SDRAM, NOR and NAND memories
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- QSPI
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- SD/MMC/SDIO support
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- Ethernet controller
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- ADC/DAC
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- USB EHCI/OHCI controllers
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- USB OTG
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- I2C, SPI busses support
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- Several general purpose timers
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- Serial Audio interface
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- LCD-TFT controller
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- DCMIPP
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- SPDIFRX
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- DFSDM
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:Authors:
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- Roan van Dijk <roan@protonic.nl>

‎arch/arm/boot/dts/stm32mp13-pinctrl.dtsi‎

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bias-disable;
259259
};
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};
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uart4_idle_pins_a: uart4-idle-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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uart4_sleep_pins_a: uart4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
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<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
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};
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};
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uart8_pins_a: uart8-0 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
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bias-pull-up;
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};
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};
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uart8_idle_pins_a: uart8-idle-0 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
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};
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pins2 {
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pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
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bias-pull-up;
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};
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};
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uart8_sleep_pins_a: uart8-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
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<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
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};
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};
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usart1_pins_a: usart1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
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<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
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<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
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bias-pull-up;
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};
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};
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usart1_idle_pins_a: usart1-idle-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
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<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
328+
};
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pins2 {
330+
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
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bias-disable;
332+
drive-push-pull;
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slew-rate = <0>;
334+
};
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pins3 {
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pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
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bias-pull-up;
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};
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};
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usart1_sleep_pins_a: usart1-sleep-0 {
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pins {
343+
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
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<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
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<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
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<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
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};
348+
};
349+
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usart2_pins_a: usart2-0 {
351+
pins1 {
352+
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
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<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
354+
bias-disable;
355+
drive-push-pull;
356+
slew-rate = <0>;
357+
};
358+
pins2 {
359+
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
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<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
361+
bias-disable;
362+
};
363+
};
364+
365+
usart2_idle_pins_a: usart2-idle-0 {
366+
pins1 {
367+
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
368+
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
369+
};
370+
pins2 {
371+
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
372+
bias-disable;
373+
drive-push-pull;
374+
slew-rate = <0>;
375+
};
376+
pins3 {
377+
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
378+
bias-disable;
379+
};
380+
};
381+
382+
usart2_sleep_pins_a: usart2-sleep-0 {
383+
pins {
384+
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
385+
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
386+
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
387+
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
388+
};
389+
};
261390
};

‎arch/arm/boot/dts/stm32mp131.dtsi‎

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397397
status = "disabled";
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};
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400+
usart3: serial@4000f000 {
401+
compatible = "st,stm32h7-uart";
402+
reg = <0x4000f000 0x400>;
403+
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
404+
clocks = <&rcc USART3_K>;
405+
resets = <&rcc USART3_R>;
406+
wakeup-source;
407+
dmas = <&dmamux1 45 0x400 0x5>,
408+
<&dmamux1 46 0x400 0x1>;
409+
dma-names = "rx", "tx";
410+
status = "disabled";
411+
};
412+
400413
uart4: serial@40010000 {
401414
compatible = "st,stm32h7-uart";
402415
reg = <0x40010000 0x400>;
403-
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
416+
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
404417
clocks = <&rcc UART4_K>;
405418
resets = <&rcc UART4_R>;
419+
wakeup-source;
420+
dmas = <&dmamux1 63 0x400 0x5>,
421+
<&dmamux1 64 0x400 0x1>;
422+
dma-names = "rx", "tx";
423+
status = "disabled";
424+
};
425+
426+
uart5: serial@40011000 {
427+
compatible = "st,stm32h7-uart";
428+
reg = <0x40011000 0x400>;
429+
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
430+
clocks = <&rcc UART5_K>;
431+
resets = <&rcc UART5_R>;
432+
wakeup-source;
433+
dmas = <&dmamux1 65 0x400 0x5>,
434+
<&dmamux1 66 0x400 0x1>;
435+
dma-names = "rx", "tx";
406436
status = "disabled";
407437
};
408438

@@ -442,6 +472,32 @@
442472
status = "disabled";
443473
};
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475+
uart7: serial@40018000 {
476+
compatible = "st,stm32h7-uart";
477+
reg = <0x40018000 0x400>;
478+
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
479+
clocks = <&rcc UART7_K>;
480+
resets = <&rcc UART7_R>;
481+
wakeup-source;
482+
dmas = <&dmamux1 79 0x400 0x5>,
483+
<&dmamux1 80 0x400 0x1>;
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dma-names = "rx", "tx";
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status = "disabled";
486+
};
487+
488+
uart8: serial@40019000 {
489+
compatible = "st,stm32h7-uart";
490+
reg = <0x40019000 0x400>;
491+
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
492+
clocks = <&rcc UART8_K>;
493+
resets = <&rcc UART8_R>;
494+
wakeup-source;
495+
dmas = <&dmamux1 81 0x400 0x5>,
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<&dmamux1 82 0x400 0x1>;
497+
dma-names = "rx", "tx";
498+
status = "disabled";
499+
};
500+
445501
timers1: timer@44000000 {
446502
#address-cells = <1>;
447503
#size-cells = <0>;
@@ -524,6 +580,19 @@
524580
};
525581
};
526582

583+
usart6: serial@44003000 {
584+
compatible = "st,stm32h7-uart";
585+
reg = <0x44003000 0x400>;
586+
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
587+
clocks = <&rcc USART6_K>;
588+
resets = <&rcc USART6_R>;
589+
wakeup-source;
590+
dmas = <&dmamux1 71 0x400 0x5>,
591+
<&dmamux1 72 0x400 0x1>;
592+
dma-names = "rx", "tx";
593+
status = "disabled";
594+
};
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527596
i2s1: audio-controller@44004000 {
528597
compatible = "st,stm32h7-i2s";
529598
reg = <0x44004000 0x400>;
@@ -748,6 +817,32 @@
748817
status = "disabled";
749818
};
750819

820+
usart1: serial@4c000000 {
821+
compatible = "st,stm32h7-uart";
822+
reg = <0x4c000000 0x400>;
823+
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
824+
clocks = <&rcc USART1_K>;
825+
resets = <&rcc USART1_R>;
826+
wakeup-source;
827+
dmas = <&dmamux1 41 0x400 0x5>,
828+
<&dmamux1 42 0x400 0x1>;
829+
dma-names = "rx", "tx";
830+
status = "disabled";
831+
};
832+
833+
usart2: serial@4c001000 {
834+
compatible = "st,stm32h7-uart";
835+
reg = <0x4c001000 0x400>;
836+
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
837+
clocks = <&rcc USART2_K>;
838+
resets = <&rcc USART2_R>;
839+
wakeup-source;
840+
dmas = <&dmamux1 43 0x400 0x5>,
841+
<&dmamux1 44 0x400 0x1>;
842+
dma-names = "rx", "tx";
843+
status = "disabled";
844+
};
845+
751846
i2s4: audio-controller@4c002000 {
752847
compatible = "st,stm32h7-i2s";
753848
reg = <0x4c002000 0x400>;
@@ -1137,6 +1232,54 @@
11371232
dma-requests = <48>;
11381233
};
11391234

1235+
fmc: memory-controller@58002000 {
1236+
compatible = "st,stm32mp1-fmc2-ebi";
1237+
reg = <0x58002000 0x1000>;
1238+
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1239+
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1240+
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1241+
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1242+
<4 0 0x80000000 0x10000000>; /* NAND */
1243+
#address-cells = <2>;
1244+
#size-cells = <1>;
1245+
clocks = <&rcc FMC_K>;
1246+
resets = <&rcc FMC_R>;
1247+
status = "disabled";
1248+
1249+
nand-controller@4,0 {
1250+
compatible = "st,stm32mp1-fmc2-nfc";
1251+
reg = <4 0x00000000 0x1000>,
1252+
<4 0x08010000 0x1000>,
1253+
<4 0x08020000 0x1000>,
1254+
<4 0x01000000 0x1000>,
1255+
<4 0x09010000 0x1000>,
1256+
<4 0x09020000 0x1000>;
1257+
#address-cells = <1>;
1258+
#size-cells = <0>;
1259+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1260+
dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1261+
<&mdma 24 0x2 0x12000a08 0x0 0x0>,
1262+
<&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1263+
dma-names = "tx", "rx", "ecc";
1264+
status = "disabled";
1265+
};
1266+
};
1267+
1268+
qspi: spi@58003000 {
1269+
compatible = "st,stm32f469-qspi";
1270+
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1271+
reg-names = "qspi", "qspi_mm";
1272+
#address-cells = <1>;
1273+
#size-cells = <0>;
1274+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1275+
dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1276+
<&mdma 26 0x2 0x10100008 0x0 0x0>;
1277+
dma-names = "tx", "rx";
1278+
clocks = <&rcc QSPI_K>;
1279+
resets = <&rcc QSPI_R>;
1280+
status = "disabled";
1281+
};
1282+
11401283
sdmmc1: mmc@58005000 {
11411284
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
11421285
arm,primecell-periphid = <0x20253180>;

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