Skip to content

Commit 893ace4

Browse files
torvaldstorvalds
committed
Merge tag 'pwrseq-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull power sequencing updates from Bartosz Golaszewski: "One new driver and support for more models added to the existing qcom-wcn driver as well as some minor tweaks and fixes. New drivers: - add the power sequencing driver for PCIe M.2 connectors Driver improvements: - use device_get_match_data() where applicable - add support for the WCN39xx family of models to pwrseq-qcom-wcn Fixes: - fix a locking issue in pwrseq core - fix retval check in pwrseq-qcom-wcn" * tag 'pwrseq-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: power: sequencing: qcom-wcn: fix error path for VDDIO handling power: sequencing: fix missing state_lock in pwrseq_power_on() error path power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector power: sequencing: qcom-wcn: add support for WCN39xx regulator: dt-bindings: qcom,wcn3990-pmu: describe PMUs on WCN39xx power: sequencing: qcom-wcn: use device_get_match_data()
2 parents c371f62 + ecfcae7 commit 893ace4

8 files changed

Lines changed: 560 additions & 8 deletions

File tree

‎Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml‎

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: PCIe M.2 Mechanical Key M Connector
8+
9+
maintainers:
10+
- Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
11+
12+
description:
13+
A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M
14+
connector. The Mechanical Key M connectors are used to connect SSDs to the
15+
host system over PCIe/SATA interfaces. These connectors also offer optional
16+
interfaces like USB, SMBus.
17+
18+
properties:
19+
compatible:
20+
const: pcie-m2-m-connector
21+
22+
vpcie3v3-supply:
23+
description: A phandle to the regulator for 3.3v supply.
24+
25+
vpcie1v8-supply:
26+
description: A phandle to the regulator for VIO 1.8v supply.
27+
28+
ports:
29+
$ref: /schemas/graph.yaml#/properties/ports
30+
description: OF graph bindings modeling the interfaces exposed on the
31+
connector. Since a single connector can have multiple interfaces, every
32+
interface has an assigned OF graph port number as described below.
33+
34+
properties:
35+
port@0:
36+
$ref: /schemas/graph.yaml#/properties/port
37+
description: PCIe interface
38+
39+
port@1:
40+
$ref: /schemas/graph.yaml#/properties/port
41+
description: SATA interface
42+
43+
port@2:
44+
$ref: /schemas/graph.yaml#/properties/port
45+
description: USB 2.0 interface
46+
47+
anyOf:
48+
- required:
49+
- port@0
50+
- required:
51+
- port@1
52+
53+
i2c-parent:
54+
$ref: /schemas/types.yaml#/definitions/phandle
55+
description: I2C interface
56+
57+
clocks:
58+
description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
59+
the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
60+
more details.
61+
maxItems: 1
62+
63+
pedet-gpios:
64+
description: GPIO input to PEDET signal. This signal is used by the host
65+
systems to determine the communication protocol that the M.2 card uses;
66+
SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2
67+
Specification r4.0, sec 3.3.4.2 for more details.
68+
maxItems: 1
69+
70+
viocfg-gpios:
71+
description: GPIO input to IO voltage configuration (VIO_CFG) signal. This
72+
signal is used by the host systems to determine whether the card supports
73+
an independent IO voltage domain for the sideband signals or not. Refer,
74+
PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
75+
maxItems: 1
76+
77+
pwrdis-gpios:
78+
description: GPIO output to Power Disable (PWRDIS) signal. This signal is
79+
used by the host system to disable power on the M.2 card. Refer, PCI
80+
Express M.2 Specification r4.0, sec 3.3.5.2 for more details.
81+
maxItems: 1
82+
83+
pln-gpios:
84+
description: GPIO output to Power Loss Notification (PLN#) signal. This
85+
signal is used by the host system to notify the M.2 card that the power
86+
loss event is about to occur. Refer, PCI Express M.2 Specification r4.0,
87+
sec 3.2.17.1 for more details.
88+
maxItems: 1
89+
90+
plas3-gpios:
91+
description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. This
92+
signal is used by the host system to receive the acknowledgment of the M.2
93+
card's preparation for power loss.
94+
maxItems: 1
95+
96+
required:
97+
- compatible
98+
- vpcie3v3-supply
99+
100+
additionalProperties: false
101+
102+
examples:
103+
# PCI M.2 Key M connector for SSDs with PCIe interface
104+
- |
105+
#include <dt-bindings/gpio/gpio.h>
106+
107+
connector {
108+
compatible = "pcie-m2-m-connector";
109+
vpcie3v3-supply = <&vreg_nvme>;
110+
i2c-parent = <&i2c0>;
111+
pedet-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
112+
viocfg-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
113+
pwrdis-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>;
114+
pln-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
115+
plas3-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
116+
117+
ports {
118+
#address-cells = <1>;
119+
#size-cells = <0>;
120+
121+
port@0 {
122+
#address-cells = <1>;
123+
#size-cells = <0>;
124+
125+
reg = <0>;
126+
127+
endpoint@0 {
128+
reg = <0>;
129+
remote-endpoint = <&pcie6_port0_ep>;
130+
};
131+
};
132+
133+
port@2 {
134+
#address-cells = <1>;
135+
#size-cells = <0>;
136+
137+
reg = <2>;
138+
139+
endpoint@0 {
140+
reg = <0>;
141+
remote-endpoint = <&usb_hs_ep>;
142+
};
143+
};
144+
};
145+
};

‎Documentation/devicetree/bindings/regulator/qcom,wcn3990-pmu.yaml‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/regulator/qcom,wcn3990-pmu.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Technologies, Inc. WCN3990 PMU Regulators
8+
9+
maintainers:
10+
- Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
11+
12+
description:
13+
The WCN3990 package contains discrete modules for WLAN and Bluetooth. They
14+
are powered by the Power Management Unit (PMU) that takes inputs from the
15+
host and provides LDO outputs. This document describes this module.
16+
17+
properties:
18+
compatible:
19+
enum:
20+
- qcom,wcn3950-pmu
21+
- qcom,wcn3988-pmu
22+
- qcom,wcn3990-pmu
23+
- qcom,wcn3991-pmu
24+
- qcom,wcn3998-pmu
25+
26+
vddio-supply:
27+
description: VDD_IO supply regulator handle
28+
29+
vddxo-supply:
30+
description: VDD_XTAL supply regulator handle
31+
32+
vddrf-supply:
33+
description: VDD_RF supply regulator handle
34+
35+
vddch0-supply:
36+
description: chain 0 supply regulator handle
37+
38+
vddch1-supply:
39+
description: chain 1 supply regulator handle
40+
41+
swctrl-gpios:
42+
maxItems: 1
43+
description: GPIO line indicating the state of the clock supply to the BT module
44+
45+
clocks:
46+
maxItems: 1
47+
description: Reference clock handle
48+
49+
regulators:
50+
type: object
51+
description:
52+
LDO outputs of the PMU
53+
54+
patternProperties:
55+
"^ldo[0-9]$":
56+
$ref: regulator.yaml#
57+
type: object
58+
unevaluatedProperties: false
59+
60+
additionalProperties: false
61+
62+
required:
63+
- compatible
64+
- regulators
65+
- vddio-supply
66+
- vddxo-supply
67+
- vddrf-supply
68+
- vddch0-supply
69+
70+
additionalProperties: false
71+
72+
examples:
73+
- |
74+
#include <dt-bindings/gpio/gpio.h>
75+
pmu {
76+
compatible = "qcom,wcn3990-pmu";
77+
78+
vddio-supply = <&vreg_io>;
79+
vddxo-supply = <&vreg_xo>;
80+
vddrf-supply = <&vreg_rf>;
81+
vddch0-supply = <&vreg_ch0>;
82+
83+
regulators {
84+
vreg_pmu_io: ldo0 {
85+
regulator-name = "vreg_pmu_io";
86+
};
87+
88+
vreg_pmu_xo: ldo1 {
89+
regulator-name = "vreg_pmu_xo";
90+
};
91+
92+
vreg_pmu_rf: ldo2 {
93+
regulator-name = "vreg_pmu_rf";
94+
};
95+
96+
vreg_pmu_ch0: ldo3 {
97+
regulator-name = "vreg_pmu_ch0";
98+
};
99+
};
100+
};

‎MAINTAINERS‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20861,6 +20861,13 @@ F: Documentation/driver-api/pwrseq.rst
2086120861
F: drivers/power/sequencing/
2086220862
F: include/linux/pwrseq/
2086320863

20864+
PCIE M.2 POWER SEQUENCING
20865+
M: Manivannan Sadhasivam <mani@kernel.org>
20866+
L: linux-pci@vger.kernel.org
20867+
S: Maintained
20868+
F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
20869+
F: drivers/power/sequencing/pwrseq-pcie-m2.c
20870+
2086420871
POWER STATE COORDINATION INTERFACE (PSCI)
2086520872
M: Mark Rutland <mark.rutland@arm.com>
2086620873
M: Lorenzo Pieralisi <lpieralisi@kernel.org>

‎drivers/power/sequencing/Kconfig‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU
3535
GPU. This driver handles the complex clock and reset sequence
3636
required to power on the Imagination BXM GPU on this platform.
3737

38+
config POWER_SEQUENCING_PCIE_M2
39+
tristate "PCIe M.2 connector power sequencing driver"
40+
depends on OF || COMPILE_TEST
41+
help
42+
Say Y here to enable the power sequencing driver for PCIe M.2
43+
connectors. This driver handles the power sequencing for the M.2
44+
connectors exposing multiple interfaces like PCIe, SATA, UART, etc...
45+
3846
endif

‎drivers/power/sequencing/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,4 @@ pwrseq-core-y := core.o
55

66
obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) += pwrseq-qcom-wcn.o
77
obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) += pwrseq-thead-gpu.o
8+
obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) += pwrseq-pcie-m2.o

‎drivers/power/sequencing/core.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -914,8 +914,10 @@ int pwrseq_power_on(struct pwrseq_desc *desc)
914914
if (target->post_enable) {
915915
ret = target->post_enable(pwrseq);
916916
if (ret) {
917-
pwrseq_unit_disable(pwrseq, unit);
918-
desc->powered_on = false;
917+
scoped_guard(mutex, &pwrseq->state_lock) {
918+
pwrseq_unit_disable(pwrseq, unit);
919+
desc->powered_on = false;
920+
}
919921
}
920922
}
921923

0 commit comments

Comments
 (0)