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Konrad Dybcioandersson
Konrad Dybcio
authored and
andersson
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clk: qcom: smd: Add missing MSM8998 RPM clocks
Add missing RPM-provided clocks on msm8998 and reorder the definitions where needed. Tested-by: Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226214126.21209-3-konrad.dybcio@somainline.org
1 parent f804360 commit 89f0f1a

1 file changed

Lines changed: 27 additions & 13 deletions

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‎drivers/clk/qcom/clk-smd-rpm.c‎

Lines changed: 27 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -816,15 +816,18 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
816816
.num_clks = ARRAY_SIZE(qcs404_clks),
817817
};
818818

819-
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
820-
3, 19200000);
819+
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
820+
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
821821
DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
822822
QCOM_SMD_RPM_AGGR_CLK, 1);
823823
DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
824824
QCOM_SMD_RPM_AGGR_CLK, 2);
825825
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
826826
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
827+
827828
static struct clk_smd_rpm *msm8998_clks[] = {
829+
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
830+
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
828831
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
829832
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
830833
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
@@ -837,12 +840,22 @@ static struct clk_smd_rpm *msm8998_clks[] = {
837840
[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
838841
[RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
839842
[RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
843+
[RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
844+
[RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
845+
[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
846+
[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
840847
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
841848
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
842849
[RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
843850
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
844851
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
845852
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
853+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
854+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
855+
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
856+
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
857+
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
858+
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
846859
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
847860
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
848861
[RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
@@ -855,10 +868,14 @@ static struct clk_smd_rpm *msm8998_clks[] = {
855868
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
856869
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
857870
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
858-
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
859-
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
871+
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
872+
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
860873
[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
861874
[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
875+
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
876+
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
877+
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
878+
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
862879
[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
863880
[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
864881
};
@@ -868,9 +885,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
868885
.num_clks = ARRAY_SIZE(msm8998_clks),
869886
};
870887

871-
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
872-
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
873-
874888
static struct clk_smd_rpm *sdm660_clks[] = {
875889
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
876890
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
@@ -900,16 +914,16 @@ static struct clk_smd_rpm *sdm660_clks[] = {
900914
[RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
901915
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
902916
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
903-
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
904-
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
917+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
918+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
905919
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
906920
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
907921
[RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
908922
[RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
909923
[RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
910924
[RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
911-
[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
912-
[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
925+
[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
926+
[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
913927
};
914928

915929
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
@@ -1011,8 +1025,8 @@ static struct clk_smd_rpm *sm6125_clks[] = {
10111025
[RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
10121026
[RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
10131027
[RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1014-
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
1015-
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
1028+
[RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
1029+
[RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
10161030
[RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
10171031
[RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
10181032
[RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,

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