Skip to content

Commit 8e1c8cc

Browse files
author
Bartosz Golaszewski
committed
gpio: sifive: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-11-f3d1a4c57124@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
1 parent b24489a commit 8e1c8cc

1 file changed

Lines changed: 38 additions & 35 deletions

File tree

‎drivers/gpio/gpio-sifive.c‎

Lines changed: 38 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <linux/device.h>
88
#include <linux/errno.h>
99
#include <linux/gpio/driver.h>
10+
#include <linux/gpio/generic.h>
1011
#include <linux/init.h>
1112
#include <linux/platform_device.h>
1213
#include <linux/property.h>
@@ -32,7 +33,7 @@
3233

3334
struct sifive_gpio {
3435
void __iomem *base;
35-
struct gpio_chip gc;
36+
struct gpio_generic_chip gen_gc;
3637
struct regmap *regs;
3738
unsigned long irq_state;
3839
unsigned int trigger[SIFIVE_GPIO_MAX];
@@ -41,10 +42,10 @@ struct sifive_gpio {
4142

4243
static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
4344
{
44-
unsigned long flags;
4545
unsigned int trigger;
4646

47-
raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
47+
guard(gpio_generic_lock_irqsave)(&chip->gen_gc);
48+
4849
trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
4950
regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
5051
(trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
@@ -54,7 +55,6 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
5455
(trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
5556
regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
5657
(trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
57-
raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
5858
}
5959

6060
static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
@@ -72,27 +72,26 @@ static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
7272
}
7373

7474
static void sifive_gpio_irq_enable(struct irq_data *d)
75-
{
75+
{
7676
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
7777
struct sifive_gpio *chip = gpiochip_get_data(gc);
7878
irq_hw_number_t hwirq = irqd_to_hwirq(d);
7979
int offset = hwirq % SIFIVE_GPIO_MAX;
8080
u32 bit = BIT(offset);
81-
unsigned long flags;
8281

8382
gpiochip_enable_irq(gc, hwirq);
8483
irq_chip_enable_parent(d);
8584

8685
/* Switch to input */
8786
gc->direction_input(gc, offset);
8887

89-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
90-
/* Clear any sticky pending interrupts */
91-
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
92-
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
93-
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
94-
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
95-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
88+
scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
89+
/* Clear any sticky pending interrupts */
90+
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
91+
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
92+
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
93+
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
94+
}
9695

9796
/* Enable interrupts */
9897
assign_bit(offset, &chip->irq_state, 1);
@@ -118,15 +117,14 @@ static void sifive_gpio_irq_eoi(struct irq_data *d)
118117
struct sifive_gpio *chip = gpiochip_get_data(gc);
119118
int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
120119
u32 bit = BIT(offset);
121-
unsigned long flags;
122120

123-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
124-
/* Clear all pending interrupts */
125-
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
126-
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
127-
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
128-
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
129-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
121+
scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
122+
/* Clear all pending interrupts */
123+
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
124+
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
125+
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
126+
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
127+
}
130128

131129
irq_chip_eoi_parent(d);
132130
}
@@ -179,6 +177,7 @@ static const struct regmap_config sifive_gpio_regmap_config = {
179177

180178
static int sifive_gpio_probe(struct platform_device *pdev)
181179
{
180+
struct gpio_generic_chip_config config;
182181
struct device *dev = &pdev->dev;
183182
struct irq_domain *parent;
184183
struct gpio_irq_chip *girq;
@@ -217,13 +216,17 @@ static int sifive_gpio_probe(struct platform_device *pdev)
217216
*/
218217
parent = irq_get_irq_data(chip->irq_number[0])->domain;
219218

220-
ret = bgpio_init(&chip->gc, dev, 4,
221-
chip->base + SIFIVE_GPIO_INPUT_VAL,
222-
chip->base + SIFIVE_GPIO_OUTPUT_VAL,
223-
NULL,
224-
chip->base + SIFIVE_GPIO_OUTPUT_EN,
225-
chip->base + SIFIVE_GPIO_INPUT_EN,
226-
BGPIOF_READ_OUTPUT_REG_SET);
219+
config = (struct gpio_generic_chip_config) {
220+
.dev = dev,
221+
.sz = 4,
222+
.dat = chip->base + SIFIVE_GPIO_INPUT_VAL,
223+
.set = chip->base + SIFIVE_GPIO_OUTPUT_VAL,
224+
.dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN,
225+
.dirin = chip->base + SIFIVE_GPIO_INPUT_EN,
226+
.flags = BGPIOF_READ_OUTPUT_REG_SET,
227+
};
228+
229+
ret = gpio_generic_chip_init(&chip->gen_gc, &config);
227230
if (ret) {
228231
dev_err(dev, "unable to init generic GPIO\n");
229232
return ret;
@@ -236,20 +239,20 @@ static int sifive_gpio_probe(struct platform_device *pdev)
236239
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
237240
chip->irq_state = 0;
238241

239-
chip->gc.base = -1;
240-
chip->gc.ngpio = ngpio;
241-
chip->gc.label = dev_name(dev);
242-
chip->gc.parent = dev;
243-
chip->gc.owner = THIS_MODULE;
244-
girq = &chip->gc.irq;
242+
chip->gen_gc.gc.base = -1;
243+
chip->gen_gc.gc.ngpio = ngpio;
244+
chip->gen_gc.gc.label = dev_name(dev);
245+
chip->gen_gc.gc.parent = dev;
246+
chip->gen_gc.gc.owner = THIS_MODULE;
247+
girq = &chip->gen_gc.gc.irq;
245248
gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
246249
girq->fwnode = dev_fwnode(dev);
247250
girq->parent_domain = parent;
248251
girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
249252
girq->handler = handle_bad_irq;
250253
girq->default_type = IRQ_TYPE_NONE;
251254

252-
return gpiochip_add_data(&chip->gc, chip);
255+
return gpiochip_add_data(&chip->gen_gc.gc, chip);
253256
}
254257

255258
static const struct of_device_id sifive_gpio_match[] = {

0 commit comments

Comments
 (0)