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soc: mediatek: add mtk-mutex support for mt8195 vdosys0
Add mtk-mutex support for mt8195 vdosys0. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Link: https://lore.kernel.org/r/20220419094143.9561-3-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Lines changed: 84 additions & 3 deletions

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‎drivers/soc/mediatek/mtk-mutex.c‎

Lines changed: 84 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@
1717
#define MT8183_MUTEX0_MOD0 0x30
1818
#define MT8183_MUTEX0_SOF0 0x2c
1919

20+
#define MT8195_DISP_MUTEX0_MOD0 0x30
21+
#define MT8195_DISP_MUTEX0_SOF 0x2c
22+
2023
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
2124
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
2225
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
9699
#define MT8173_MUTEX_MOD_DISP_PWM1 24
97100
#define MT8173_MUTEX_MOD_DISP_OD 25
98101

102+
#define MT8195_MUTEX_MOD_DISP_OVL0 0
103+
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
104+
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
105+
#define MT8195_MUTEX_MOD_DISP_COLOR0 3
106+
#define MT8195_MUTEX_MOD_DISP_CCORR0 4
107+
#define MT8195_MUTEX_MOD_DISP_AAL0 5
108+
#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
109+
#define MT8195_MUTEX_MOD_DISP_DITHER0 7
110+
#define MT8195_MUTEX_MOD_DISP_DSI0 8
111+
#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
112+
#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
113+
#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
114+
#define MT8195_MUTEX_MOD_DISP_PWM0 27
115+
99116
#define MT2712_MUTEX_MOD_DISP_PWM2 10
100117
#define MT2712_MUTEX_MOD_DISP_OVL0 11
101118
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
132149
#define MT8167_MUTEX_SOF_DPI1 3
133150
#define MT8183_MUTEX_SOF_DSI0 1
134151
#define MT8183_MUTEX_SOF_DPI0 2
152+
#define MT8195_MUTEX_SOF_DSI0 1
153+
#define MT8195_MUTEX_SOF_DSI1 2
154+
#define MT8195_MUTEX_SOF_DP_INTF0 3
155+
#define MT8195_MUTEX_SOF_DP_INTF1 4
156+
#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
157+
#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
135158

136159
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
137160
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
161+
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
162+
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
163+
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
164+
#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
165+
#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
166+
#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
138167

139168
struct mtk_mutex {
140169
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
149178
MUTEX_SOF_DPI1,
150179
MUTEX_SOF_DSI2,
151180
MUTEX_SOF_DSI3,
181+
MUTEX_SOF_DP_INTF0,
182+
MUTEX_SOF_DP_INTF1,
183+
DDP_MUTEX_SOF_MAX,
152184
};
153185

154186
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
270302
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
271303
};
272304

273-
static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
305+
static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
306+
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
307+
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
308+
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
309+
[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
310+
[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
311+
[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
312+
[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
313+
[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
314+
[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
315+
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
316+
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
317+
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
318+
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
319+
};
320+
321+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
274322
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
275323
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
276324
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,15 +328,15 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
280328
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
281329
};
282330

283-
static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
331+
static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
284332
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
285333
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
286334
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
287335
[MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
288336
};
289337

290338
/* Add EOF setting so overlay hardware can receive frame done irq */
291-
static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
339+
static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
292340
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
293341
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
294342
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
300348
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
301349
};
302350

351+
/*
352+
* To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
353+
* select the EOF source and configure the EOF plus timing from the
354+
* module that provides the timing signal.
355+
* So that MUTEX can not only send a STREAM_DONE event to GCE
356+
* but also detect the error at end of frame(EAEOF) when EOF signal
357+
* arrives.
358+
*/
359+
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
360+
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
361+
[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
362+
[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
363+
[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
364+
[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
365+
[MUTEX_SOF_DP_INTF0] =
366+
MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
367+
[MUTEX_SOF_DP_INTF1] =
368+
MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
369+
};
370+
303371
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
304372
.mutex_mod = mt2701_mutex_mod,
305373
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
351419
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
352420
};
353421

422+
static const struct mtk_mutex_data mt8195_mutex_driver_data = {
423+
.mutex_mod = mt8195_mutex_mod,
424+
.mutex_sof = mt8195_mutex_sof,
425+
.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
426+
.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
427+
};
428+
354429
struct mtk_mutex *mtk_mutex_get(struct device *dev)
355430
{
356431
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
423498
case DDP_COMPONENT_DPI1:
424499
sof_id = MUTEX_SOF_DPI1;
425500
break;
501+
case DDP_COMPONENT_DP_INTF0:
502+
sof_id = MUTEX_SOF_DP_INTF0;
503+
break;
426504
default:
427505
if (mtx->data->mutex_mod[id] < 32) {
428506
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
462540
case DDP_COMPONENT_DSI3:
463541
case DDP_COMPONENT_DPI0:
464542
case DDP_COMPONENT_DPI1:
543+
case DDP_COMPONENT_DP_INTF0:
465544
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
466545
mtx->regs +
467546
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
587666
.data = &mt8186_mutex_driver_data},
588667
{ .compatible = "mediatek,mt8192-disp-mutex",
589668
.data = &mt8192_mutex_driver_data},
669+
{ .compatible = "mediatek,mt8195-disp-mutex",
670+
.data = &mt8195_mutex_driver_data},
590671
{},
591672
};
592673
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);

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