@@ -28,6 +28,61 @@ extern bool hang_debug;
2828static void a3xx_dump (struct msm_gpu * gpu );
2929static bool a3xx_idle (struct msm_gpu * gpu );
3030
31+ static void a3xx_submit (struct msm_gpu * gpu , struct msm_gem_submit * submit )
32+ {
33+ struct msm_drm_private * priv = gpu -> dev -> dev_private ;
34+ struct msm_ringbuffer * ring = submit -> ring ;
35+ unsigned int i ;
36+
37+ for (i = 0 ; i < submit -> nr_cmds ; i ++ ) {
38+ switch (submit -> cmd [i ].type ) {
39+ case MSM_SUBMIT_CMD_IB_TARGET_BUF :
40+ /* ignore IB-targets */
41+ break ;
42+ case MSM_SUBMIT_CMD_CTX_RESTORE_BUF :
43+ /* ignore if there has not been a ctx switch: */
44+ if (priv -> lastctx == submit -> queue -> ctx )
45+ break ;
46+ fallthrough ;
47+ case MSM_SUBMIT_CMD_BUF :
48+ OUT_PKT3 (ring , CP_INDIRECT_BUFFER_PFD , 2 );
49+ OUT_RING (ring , lower_32_bits (submit -> cmd [i ].iova ));
50+ OUT_RING (ring , submit -> cmd [i ].size );
51+ OUT_PKT2 (ring );
52+ break ;
53+ }
54+ }
55+
56+ OUT_PKT0 (ring , REG_AXXX_CP_SCRATCH_REG2 , 1 );
57+ OUT_RING (ring , submit -> seqno );
58+
59+ /* Flush HLSQ lazy updates to make sure there is nothing
60+ * pending for indirect loads after the timestamp has
61+ * passed:
62+ */
63+ OUT_PKT3 (ring , CP_EVENT_WRITE , 1 );
64+ OUT_RING (ring , HLSQ_FLUSH );
65+
66+ /* wait for idle before cache flush/interrupt */
67+ OUT_PKT3 (ring , CP_WAIT_FOR_IDLE , 1 );
68+ OUT_RING (ring , 0x00000000 );
69+
70+ /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
71+ OUT_PKT3 (ring , CP_EVENT_WRITE , 3 );
72+ OUT_RING (ring , CACHE_FLUSH_TS | BIT (31 ));
73+ OUT_RING (ring , rbmemptr (ring , fence ));
74+ OUT_RING (ring , submit -> seqno );
75+
76+ #if 0
77+ /* Dummy set-constant to trigger context rollover */
78+ OUT_PKT3 (ring , CP_SET_CONSTANT , 2 );
79+ OUT_RING (ring , CP_REG (REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG ));
80+ OUT_RING (ring , 0x00000000 );
81+ #endif
82+
83+ adreno_flush (gpu , ring , REG_AXXX_CP_RB_WPTR );
84+ }
85+
3186static bool a3xx_me_init (struct msm_gpu * gpu )
3287{
3388 struct msm_ringbuffer * ring = gpu -> rb [0 ];
@@ -51,7 +106,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
51106 OUT_RING (ring , 0x00000000 );
52107 OUT_RING (ring , 0x00000000 );
53108
54- gpu -> funcs -> flush (gpu , ring );
109+ adreno_flush (gpu , ring , REG_AXXX_CP_RB_WPTR );
55110 return a3xx_idle (gpu );
56111}
57112
@@ -423,16 +478,11 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)
423478 return state ;
424479}
425480
426- /* Register offset defines for A3XX */
427- static const unsigned int a3xx_register_offsets [REG_ADRENO_REGISTER_MAX ] = {
428- REG_ADRENO_DEFINE (REG_ADRENO_CP_RB_BASE , REG_AXXX_CP_RB_BASE ),
429- REG_ADRENO_SKIP (REG_ADRENO_CP_RB_BASE_HI ),
430- REG_ADRENO_DEFINE (REG_ADRENO_CP_RB_RPTR_ADDR , REG_AXXX_CP_RB_RPTR_ADDR ),
431- REG_ADRENO_SKIP (REG_ADRENO_CP_RB_RPTR_ADDR_HI ),
432- REG_ADRENO_DEFINE (REG_ADRENO_CP_RB_RPTR , REG_AXXX_CP_RB_RPTR ),
433- REG_ADRENO_DEFINE (REG_ADRENO_CP_RB_WPTR , REG_AXXX_CP_RB_WPTR ),
434- REG_ADRENO_DEFINE (REG_ADRENO_CP_RB_CNTL , REG_AXXX_CP_RB_CNTL ),
435- };
481+ static u32 a3xx_get_rptr (struct msm_gpu * gpu , struct msm_ringbuffer * ring )
482+ {
483+ ring -> memptrs -> rptr = gpu_read (gpu , REG_AXXX_CP_RB_RPTR );
484+ return ring -> memptrs -> rptr ;
485+ }
436486
437487static const struct adreno_gpu_funcs funcs = {
438488 .base = {
@@ -441,8 +491,7 @@ static const struct adreno_gpu_funcs funcs = {
441491 .pm_suspend = msm_gpu_pm_suspend ,
442492 .pm_resume = msm_gpu_pm_resume ,
443493 .recover = a3xx_recover ,
444- .submit = adreno_submit ,
445- .flush = adreno_flush ,
494+ .submit = a3xx_submit ,
446495 .active_ring = adreno_active_ring ,
447496 .irq = a3xx_irq ,
448497 .destroy = a3xx_destroy ,
@@ -452,6 +501,7 @@ static const struct adreno_gpu_funcs funcs = {
452501 .gpu_state_get = a3xx_gpu_state_get ,
453502 .gpu_state_put = adreno_gpu_state_put ,
454503 .create_address_space = adreno_iommu_create_address_space ,
504+ .get_rptr = a3xx_get_rptr ,
455505 },
456506};
457507
@@ -490,7 +540,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
490540 gpu -> num_perfcntrs = ARRAY_SIZE (perfcntrs );
491541
492542 adreno_gpu -> registers = a3xx_registers ;
493- adreno_gpu -> reg_offsets = a3xx_register_offsets ;
494543
495544 ret = adreno_gpu_init (dev , pdev , adreno_gpu , & funcs , 1 );
496545 if (ret )
0 commit comments