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phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-4-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Lines changed: 31 additions & 31 deletions

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‎drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c‎

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -32,17 +32,17 @@
3232
#define HDPTX_O_PHY_RDY BIT(1)
3333
#define HDPTX_O_SB_RDY BIT(0)
3434

35-
#define HDTPX_REG(_n, _min, _max) \
35+
#define HDPTX_REG(_n, _min, _max) \
3636
( \
3737
BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
3838
BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
3939
((0x##_n) * 4) \
4040
)
4141

42-
#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
43-
#define SB_REG(n) HDTPX_REG(n, 0100, 0129)
44-
#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
45-
#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
42+
#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7)
43+
#define SB_REG(n) HDPTX_REG(n, 0100, 0129)
44+
#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229)
45+
#define LANE_REG(n) HDPTX_REG(n, 0300, 062d)
4646

4747
/* CMN_REG(0008) */
4848
#define OVRD_LCPLL_EN_MASK BIT(7)
@@ -397,7 +397,7 @@ struct rk_hdptx_phy {
397397
unsigned int lanes;
398398
};
399399

400-
static const struct ropll_config ropll_tmds_cfg[] = {
400+
static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
401401
/* | pms | sdm | sdc | */
402402
/* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, num, deno, */
403403
{ 594000000ULL, 124, 124, 1, 1, 0, 1, 62, 1, 16, 5, 0, 1, },
@@ -424,7 +424,7 @@ static const struct ropll_config ropll_tmds_cfg[] = {
424424
{ 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, 1, 1, },
425425
};
426426

427-
static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
427+
static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
428428
REG_SEQ0(CMN_REG(0009), 0x0c),
429429
REG_SEQ0(CMN_REG(000a), 0x83),
430430
REG_SEQ0(CMN_REG(000b), 0x06),
@@ -514,7 +514,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
514514
REG_SEQ0(CMN_REG(009b), 0x10),
515515
};
516516

517-
static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
517+
static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
518518
REG_SEQ0(CMN_REG(0008), 0x00),
519519
REG_SEQ0(CMN_REG(0011), 0x01),
520520
REG_SEQ0(CMN_REG(0017), 0x20),
@@ -556,30 +556,30 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
556556
REG_SEQ0(CMN_REG(009b), 0x00),
557557
};
558558

559-
static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
559+
static const struct reg_sequence rk_hdptx_common_sb_init_seq[] = {
560560
REG_SEQ0(SB_REG(0114), 0x00),
561561
REG_SEQ0(SB_REG(0115), 0x00),
562562
REG_SEQ0(SB_REG(0116), 0x00),
563563
REG_SEQ0(SB_REG(0117), 0x00),
564564
};
565565

566-
static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
566+
static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] = {
567567
REG_SEQ0(LNTOP_REG(0201), 0x00),
568568
REG_SEQ0(LNTOP_REG(0202), 0x00),
569569
REG_SEQ0(LNTOP_REG(0203), 0x0f),
570570
REG_SEQ0(LNTOP_REG(0204), 0xff),
571571
REG_SEQ0(LNTOP_REG(0205), 0xff),
572572
};
573573

574-
static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
574+
static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] = {
575575
REG_SEQ0(LNTOP_REG(0201), 0x07),
576576
REG_SEQ0(LNTOP_REG(0202), 0xc1),
577577
REG_SEQ0(LNTOP_REG(0203), 0xf0),
578578
REG_SEQ0(LNTOP_REG(0204), 0x7c),
579579
REG_SEQ0(LNTOP_REG(0205), 0x1f),
580580
};
581581

582-
static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
582+
static const struct reg_sequence rk_hdptx_common_lane_init_seq[] = {
583583
REG_SEQ0(LANE_REG(0303), 0x0c),
584584
REG_SEQ0(LANE_REG(0307), 0x20),
585585
REG_SEQ0(LANE_REG(030a), 0x17),
@@ -634,7 +634,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
634634
REG_SEQ0(LANE_REG(0620), 0xa0),
635635
};
636636

637-
static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
637+
static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] = {
638638
REG_SEQ0(LANE_REG(0312), 0x00),
639639
REG_SEQ0(LANE_REG(0412), 0x00),
640640
REG_SEQ0(LANE_REG(0512), 0x00),
@@ -938,7 +938,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
938938
return true;
939939
}
940940

941-
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
941+
static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
942942
{
943943
const struct ropll_config *cfg = NULL;
944944
struct ropll_config rc = {0};
@@ -947,9 +947,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
947947
if (!hdptx->hdmi_cfg.tmds_char_rate)
948948
return 0;
949949

950-
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
951-
if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
952-
cfg = &ropll_tmds_cfg[i];
950+
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
951+
if (hdptx->hdmi_cfg.tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
952+
cfg = &rk_hdptx_tmds_ropll_cfg[i];
953953
break;
954954
}
955955

@@ -969,8 +969,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
969969

970970
rk_hdptx_pre_power_up(hdptx);
971971

972-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
973-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
972+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
973+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq);
974974

975975
regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
976976
regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
@@ -1012,25 +1012,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
10121012
return ret;
10131013
}
10141014

1015-
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
1015+
static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
10161016
{
1017-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
1017+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
10181018

10191019
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
10201020

10211021
if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
10221022
/* For 1/40 bitrate clk */
1023-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
1023+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq);
10241024
} else {
10251025
/* For 1/10 bitrate clk */
1026-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
1026+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq);
10271027
}
10281028

10291029
regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
10301030
regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
10311031

1032-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
1033-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
1032+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
1033+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
10341034

10351035
return rk_hdptx_post_enable_lane(hdptx);
10361036
}
@@ -1089,7 +1089,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
10891089
if (mode == PHY_MODE_DP) {
10901090
rk_hdptx_dp_reset(hdptx);
10911091
} else {
1092-
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
1092+
ret = rk_hdptx_tmds_ropll_cmn_config(hdptx);
10931093
if (ret)
10941094
goto dec_usage;
10951095
}
@@ -1436,7 +1436,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
14361436
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
14371437
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
14381438

1439-
ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
1439+
ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
14401440
if (ret)
14411441
rk_hdptx_phy_consumer_put(hdptx, true);
14421442
}
@@ -1459,11 +1459,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
14591459
if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
14601460
return -EINVAL;
14611461

1462-
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1463-
if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate)
1462+
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
1463+
if (hdmi->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
14641464
break;
14651465

1466-
if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
1466+
if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
14671467
!rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
14681468
return -EINVAL;
14691469

@@ -1891,7 +1891,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
18911891
* while the latter being executed only once, i.e. when clock remains
18921892
* in the prepared state during rate changes.
18931893
*/
1894-
return rk_hdptx_ropll_tmds_cmn_config(hdptx);
1894+
return rk_hdptx_tmds_ropll_cmn_config(hdptx);
18951895
}
18961896

18971897
static const struct clk_ops hdptx_phy_clk_ops = {

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