Skip to content

Commit aacb071

Browse files
ZideChen0Peter Zijlstra
ZideChen0
authored and
Peter Zijlstra
committed
perf/x86/intel/uncore: Support uncore constraint ranges
Add UNCORE_EVENT_CONSTRAINT_RANGE macro for uncore constraints, similar to INTEL_EVENT_CONSTRAINT_RANGE, to reduce duplication when defining consecutive uncore event constraints. No functional change intended. Suggested-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251231224233.113839-10-zide.chen@intel.com
1 parent d898704 commit aacb071

3 files changed

Lines changed: 44 additions & 143 deletions

File tree

‎arch/x86/events/intel/uncore.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -436,7 +436,7 @@ uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *eve
436436

437437
if (type->constraints) {
438438
for_each_event_constraint(c, type->constraints) {
439-
if ((event->hw.config & c->cmask) == c->code)
439+
if (constraint_match(c, event->hw.config))
440440
return c;
441441
}
442442
}

‎arch/x86/events/intel/uncore.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,8 @@
3333
#define UNCORE_EXTRA_PCI_DEV_MAX 4
3434

3535
#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
36+
#define UNCORE_EVENT_CONSTRAINT_RANGE(c, e, n) \
37+
EVENT_CONSTRAINT_RANGE(c, e, n, 0xff)
3638

3739
#define UNCORE_IGNORE_END -1
3840

‎arch/x86/events/intel/uncore_snbep.c‎

Lines changed: 41 additions & 142 deletions
Original file line numberDiff line numberDiff line change
@@ -836,76 +836,37 @@ static struct intel_uncore_ops snbep_uncore_pci_ops = {
836836
static struct event_constraint snbep_uncore_cbox_constraints[] = {
837837
UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
838838
UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
839-
UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
840-
UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
839+
UNCORE_EVENT_CONSTRAINT_RANGE(0x04, 0x5, 0x3),
841840
UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
842841
UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
843842
UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
844-
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
845-
UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
846-
UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
847-
UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
848-
UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
849-
UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
843+
UNCORE_EVENT_CONSTRAINT_RANGE(0x12, 0x13, 0x3),
844+
UNCORE_EVENT_CONSTRAINT_RANGE(0x1b, 0x1e, 0xc),
850845
UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
851846
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
852847
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
853-
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
854-
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
855-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
856-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
857-
UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
848+
UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x35, 0x3),
858849
UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
859-
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
860-
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
861-
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
850+
UNCORE_EVENT_CONSTRAINT_RANGE(0x37, 0x39, 0x3),
862851
UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
863852
EVENT_CONSTRAINT_END
864853
};
865854

866855
static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
867-
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
868-
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
856+
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
869857
UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
870858
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
871-
UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
872-
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
873-
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
874-
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
875-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
876-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
859+
UNCORE_EVENT_CONSTRAINT_RANGE(0x24, 0x26, 0x3),
860+
UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x34, 0x3),
877861
EVENT_CONSTRAINT_END
878862
};
879863

880864
static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
881-
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
882-
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
883-
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
865+
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
884866
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
885-
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
886-
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
887-
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
888-
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
889-
UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
890-
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
891-
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
892-
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
893-
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
894-
UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
895-
UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
896-
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
897-
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
898-
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
899-
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
900-
UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
901-
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
902-
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
903-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
904-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
905-
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
906-
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
907-
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
908-
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
867+
UNCORE_EVENT_CONSTRAINT_RANGE(0x20, 0x26, 0x3),
868+
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x34, 0x3),
869+
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
909870
EVENT_CONSTRAINT_END
910871
};
911872

@@ -3034,24 +2995,15 @@ static struct intel_uncore_type hswep_uncore_qpi = {
30342995
};
30352996

30362997
static struct event_constraint hswep_uncore_r2pcie_constraints[] = {
3037-
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3038-
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2998+
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
30392999
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3040-
UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
3041-
UNCORE_EVENT_CONSTRAINT(0x24, 0x1),
3042-
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
3000+
UNCORE_EVENT_CONSTRAINT_RANGE(0x23, 0x25, 0x1),
30433001
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
30443002
UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
3045-
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3046-
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3003+
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
30473004
UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
3048-
UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
3049-
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3050-
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3051-
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
3052-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3053-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3054-
UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
3005+
UNCORE_EVENT_CONSTRAINT_RANGE(0x2b, 0x2d, 0x3),
3006+
UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x35, 0x3),
30553007
EVENT_CONSTRAINT_END
30563008
};
30573009

@@ -3066,38 +3018,17 @@ static struct intel_uncore_type hswep_uncore_r2pcie = {
30663018

30673019
static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
30683020
UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
3069-
UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
3070-
UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
3071-
UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
3072-
UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
3021+
UNCORE_EVENT_CONSTRAINT_RANGE(0x7, 0x0a, 0x7),
30733022
UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3074-
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3075-
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3076-
UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
3023+
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3),
30773024
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3078-
UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
3079-
UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
3080-
UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
3081-
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
3082-
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
3083-
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
3084-
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
3085-
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
3086-
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3087-
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3088-
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3089-
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3090-
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3091-
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
3092-
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
3093-
UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
3094-
UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
3095-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3096-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3097-
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
3098-
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
3099-
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
3100-
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
3025+
UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
3026+
UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
3027+
UNCORE_EVENT_CONSTRAINT_RANGE(0x25, 0x26, 0x3),
3028+
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
3029+
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
3030+
UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x34, 0x3),
3031+
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
31013032
EVENT_CONSTRAINT_END
31023033
};
31033034

@@ -3371,8 +3302,7 @@ static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
33713302
UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
33723303
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
33733304
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3374-
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3375-
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3305+
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2d, 0x3),
33763306
EVENT_CONSTRAINT_END
33773307
};
33783308

@@ -3387,35 +3317,18 @@ static struct intel_uncore_type bdx_uncore_r2pcie = {
33873317

33883318
static struct event_constraint bdx_uncore_r3qpi_constraints[] = {
33893319
UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
3390-
UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
3391-
UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
3392-
UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
3393-
UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
3320+
UNCORE_EVENT_CONSTRAINT_RANGE(0x07, 0x0a, 0x7),
33943321
UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3395-
UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3396-
UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3322+
UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3),
33973323
UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3398-
UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
3399-
UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
3400-
UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
3401-
UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
3402-
UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
3403-
UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
3404-
UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
3324+
UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3),
3325+
UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3),
34053326
UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
34063327
UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3407-
UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3408-
UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3409-
UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3410-
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3411-
UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
3412-
UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
3413-
UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3414-
UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3415-
UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
3416-
UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
3417-
UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
3418-
UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
3328+
UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3),
3329+
UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3),
3330+
UNCORE_EVENT_CONSTRAINT_RANGE(0x33, 0x34, 0x3),
3331+
UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3),
34193332
EVENT_CONSTRAINT_END
34203333
};
34213334

@@ -3722,8 +3635,7 @@ static struct event_constraint skx_uncore_iio_constraints[] = {
37223635
UNCORE_EVENT_CONSTRAINT(0x95, 0xc),
37233636
UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
37243637
UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
3725-
UNCORE_EVENT_CONSTRAINT(0xd4, 0xc),
3726-
UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
3638+
UNCORE_EVENT_CONSTRAINT_RANGE(0xd4, 0xd5, 0xc),
37273639
EVENT_CONSTRAINT_END
37283640
};
37293641

@@ -4479,14 +4391,9 @@ static struct intel_uncore_type skx_uncore_m2pcie = {
44794391
};
44804392

44814393
static struct event_constraint skx_uncore_m3upi_constraints[] = {
4482-
UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
4483-
UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
4394+
UNCORE_EVENT_CONSTRAINT_RANGE(0x1d, 0x1e, 0x1),
44844395
UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
4485-
UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
4486-
UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
4487-
UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
4488-
UNCORE_EVENT_CONSTRAINT(0x51, 0x7),
4489-
UNCORE_EVENT_CONSTRAINT(0x52, 0x7),
4396+
UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x52, 0x7),
44904397
EVENT_CONSTRAINT_END
44914398
};
44924399

@@ -5652,14 +5559,9 @@ static struct intel_uncore_type icx_uncore_upi = {
56525559
};
56535560

56545561
static struct event_constraint icx_uncore_m3upi_constraints[] = {
5655-
UNCORE_EVENT_CONSTRAINT(0x1c, 0x1),
5656-
UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
5657-
UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
5658-
UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
5562+
UNCORE_EVENT_CONSTRAINT_RANGE(0x1c, 0x1f, 0x1),
56595563
UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
5660-
UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
5661-
UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
5662-
UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
5564+
UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x50, 0x7),
56635565
EVENT_CONSTRAINT_END
56645566
};
56655567

@@ -6142,10 +6044,7 @@ static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = {
61426044
static struct event_constraint spr_uncore_cxlcm_constraints[] = {
61436045
UNCORE_EVENT_CONSTRAINT(0x02, 0x0f),
61446046
UNCORE_EVENT_CONSTRAINT(0x05, 0x0f),
6145-
UNCORE_EVENT_CONSTRAINT(0x40, 0xf0),
6146-
UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
6147-
UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
6148-
UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
6047+
UNCORE_EVENT_CONSTRAINT_RANGE(0x40, 0x43, 0xf0),
61496048
UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
61506049
UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
61516050
EVENT_CONSTRAINT_END

0 commit comments

Comments
 (0)