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Gabriel-Fernandzbebarino
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clk: stm32mp13: add all STM32MP13 peripheral clocks
All peripheral clocks are mainly based on stm32_gate clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-9-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/stm32/clk-stm32mp13.c‎

Lines changed: 360 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -537,6 +537,303 @@ static const char * const mco2_src[] = {
537537
"ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
538538
};
539539

540+
/* Timer clocks */
541+
static struct clk_stm32_gate tim2_k = {
542+
.gate_id = GATE_TIM2,
543+
.hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
544+
};
545+
546+
static struct clk_stm32_gate tim3_k = {
547+
.gate_id = GATE_TIM3,
548+
.hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
549+
};
550+
551+
static struct clk_stm32_gate tim4_k = {
552+
.gate_id = GATE_TIM4,
553+
.hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
554+
};
555+
556+
static struct clk_stm32_gate tim5_k = {
557+
.gate_id = GATE_TIM5,
558+
.hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
559+
};
560+
561+
static struct clk_stm32_gate tim6_k = {
562+
.gate_id = GATE_TIM6,
563+
.hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
564+
};
565+
566+
static struct clk_stm32_gate tim7_k = {
567+
.gate_id = GATE_TIM7,
568+
.hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
569+
};
570+
571+
static struct clk_stm32_gate tim1_k = {
572+
.gate_id = GATE_TIM1,
573+
.hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
574+
};
575+
576+
static struct clk_stm32_gate tim8_k = {
577+
.gate_id = GATE_TIM8,
578+
.hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
579+
};
580+
581+
static struct clk_stm32_gate tim12_k = {
582+
.gate_id = GATE_TIM12,
583+
.hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
584+
};
585+
586+
static struct clk_stm32_gate tim13_k = {
587+
.gate_id = GATE_TIM13,
588+
.hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
589+
};
590+
591+
static struct clk_stm32_gate tim14_k = {
592+
.gate_id = GATE_TIM14,
593+
.hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
594+
};
595+
596+
static struct clk_stm32_gate tim15_k = {
597+
.gate_id = GATE_TIM15,
598+
.hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
599+
};
600+
601+
static struct clk_stm32_gate tim16_k = {
602+
.gate_id = GATE_TIM16,
603+
.hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
604+
};
605+
606+
static struct clk_stm32_gate tim17_k = {
607+
.gate_id = GATE_TIM17,
608+
.hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
609+
};
610+
611+
/* Peripheral clocks */
612+
static struct clk_stm32_gate sai1 = {
613+
.gate_id = GATE_SAI1,
614+
.hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
615+
};
616+
617+
static struct clk_stm32_gate sai2 = {
618+
.gate_id = GATE_SAI2,
619+
.hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
620+
};
621+
622+
static struct clk_stm32_gate syscfg = {
623+
.gate_id = GATE_SYSCFG,
624+
.hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
625+
};
626+
627+
static struct clk_stm32_gate vref = {
628+
.gate_id = GATE_VREF,
629+
.hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
630+
};
631+
632+
static struct clk_stm32_gate dts = {
633+
.gate_id = GATE_DTS,
634+
.hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
635+
};
636+
637+
static struct clk_stm32_gate pmbctrl = {
638+
.gate_id = GATE_PMBCTRL,
639+
.hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
640+
};
641+
642+
static struct clk_stm32_gate hdp = {
643+
.gate_id = GATE_HDP,
644+
.hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
645+
};
646+
647+
static struct clk_stm32_gate iwdg2 = {
648+
.gate_id = GATE_IWDG2APB,
649+
.hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
650+
};
651+
652+
static struct clk_stm32_gate stgenro = {
653+
.gate_id = GATE_STGENRO,
654+
.hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
655+
};
656+
657+
static struct clk_stm32_gate gpioa = {
658+
.gate_id = GATE_GPIOA,
659+
.hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
660+
};
661+
662+
static struct clk_stm32_gate gpiob = {
663+
.gate_id = GATE_GPIOB,
664+
.hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
665+
};
666+
667+
static struct clk_stm32_gate gpioc = {
668+
.gate_id = GATE_GPIOC,
669+
.hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
670+
};
671+
672+
static struct clk_stm32_gate gpiod = {
673+
.gate_id = GATE_GPIOD,
674+
.hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
675+
};
676+
677+
static struct clk_stm32_gate gpioe = {
678+
.gate_id = GATE_GPIOE,
679+
.hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
680+
};
681+
682+
static struct clk_stm32_gate gpiof = {
683+
.gate_id = GATE_GPIOF,
684+
.hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
685+
};
686+
687+
static struct clk_stm32_gate gpiog = {
688+
.gate_id = GATE_GPIOG,
689+
.hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
690+
};
691+
692+
static struct clk_stm32_gate gpioh = {
693+
.gate_id = GATE_GPIOH,
694+
.hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
695+
};
696+
697+
static struct clk_stm32_gate gpioi = {
698+
.gate_id = GATE_GPIOI,
699+
.hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
700+
};
701+
702+
static struct clk_stm32_gate tsc = {
703+
.gate_id = GATE_TSC,
704+
.hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
705+
};
706+
707+
static struct clk_stm32_gate ddrperfm = {
708+
.gate_id = GATE_DDRPERFM,
709+
.hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
710+
};
711+
712+
static struct clk_stm32_gate tzpc = {
713+
.gate_id = GATE_TZC,
714+
.hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
715+
};
716+
717+
static struct clk_stm32_gate iwdg1 = {
718+
.gate_id = GATE_IWDG1APB,
719+
.hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
720+
};
721+
722+
static struct clk_stm32_gate bsec = {
723+
.gate_id = GATE_BSEC,
724+
.hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
725+
};
726+
727+
static struct clk_stm32_gate dma1 = {
728+
.gate_id = GATE_DMA1,
729+
.hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
730+
};
731+
732+
static struct clk_stm32_gate dma2 = {
733+
.gate_id = GATE_DMA2,
734+
.hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
735+
};
736+
737+
static struct clk_stm32_gate dmamux1 = {
738+
.gate_id = GATE_DMAMUX1,
739+
.hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
740+
};
741+
742+
static struct clk_stm32_gate dma3 = {
743+
.gate_id = GATE_DMA3,
744+
.hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
745+
};
746+
747+
static struct clk_stm32_gate dmamux2 = {
748+
.gate_id = GATE_DMAMUX2,
749+
.hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
750+
};
751+
752+
static struct clk_stm32_gate adc1 = {
753+
.gate_id = GATE_ADC1,
754+
.hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
755+
};
756+
757+
static struct clk_stm32_gate adc2 = {
758+
.gate_id = GATE_ADC2,
759+
.hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
760+
};
761+
762+
static struct clk_stm32_gate pka = {
763+
.gate_id = GATE_PKA,
764+
.hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
765+
};
766+
767+
static struct clk_stm32_gate cryp1 = {
768+
.gate_id = GATE_CRYP1,
769+
.hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
770+
};
771+
772+
static struct clk_stm32_gate hash1 = {
773+
.gate_id = GATE_HASH1,
774+
.hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
775+
};
776+
777+
static struct clk_stm32_gate bkpsram = {
778+
.gate_id = GATE_BKPSRAM,
779+
.hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
780+
};
781+
782+
static struct clk_stm32_gate mdma = {
783+
.gate_id = GATE_MDMA,
784+
.hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
785+
};
786+
787+
static struct clk_stm32_gate eth1tx = {
788+
.gate_id = GATE_ETH1TX,
789+
.hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
790+
};
791+
792+
static struct clk_stm32_gate eth1rx = {
793+
.gate_id = GATE_ETH1RX,
794+
.hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
795+
};
796+
797+
static struct clk_stm32_gate eth1mac = {
798+
.gate_id = GATE_ETH1MAC,
799+
.hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
800+
};
801+
802+
static struct clk_stm32_gate eth2tx = {
803+
.gate_id = GATE_ETH2TX,
804+
.hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
805+
};
806+
807+
static struct clk_stm32_gate eth2rx = {
808+
.gate_id = GATE_ETH2RX,
809+
.hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
810+
};
811+
812+
static struct clk_stm32_gate eth2mac = {
813+
.gate_id = GATE_ETH2MAC,
814+
.hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
815+
};
816+
817+
static struct clk_stm32_gate crc1 = {
818+
.gate_id = GATE_CRC1,
819+
.hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
820+
};
821+
822+
static struct clk_stm32_gate usbh = {
823+
.gate_id = GATE_USBH,
824+
.hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
825+
};
826+
827+
static struct clk_stm32_gate eth1stp = {
828+
.gate_id = GATE_ETH1STP,
829+
.hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
830+
};
831+
832+
static struct clk_stm32_gate eth2stp = {
833+
.gate_id = GATE_ETH2STP,
834+
.hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
835+
};
836+
540837
static struct clk_stm32_mux ck_ker_eth1 = {
541838
.mux_id = MUX_ETH1,
542839
.hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
@@ -573,6 +870,69 @@ static struct clk_stm32_composite ck_mco2 = {
573870
};
574871

575872
static const struct clock_config stm32mp13_clock_cfg[] = {
873+
/* Timer clocks */
874+
STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
875+
STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
876+
STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
877+
STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
878+
STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
879+
STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
880+
STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
881+
STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
882+
STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
883+
STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
884+
STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
885+
STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
886+
STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
887+
STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
888+
889+
/* Peripheral clocks */
890+
STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
891+
STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
892+
STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
893+
STM32_GATE_CFG(VREF, vref, SECF_VREF),
894+
STM32_GATE_CFG(DTS, dts, SECF_NONE),
895+
STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
896+
STM32_GATE_CFG(HDP, hdp, SECF_NONE),
897+
STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
898+
STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
899+
STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
900+
STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
901+
STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
902+
STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
903+
STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
904+
STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
905+
STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
906+
STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
907+
STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
908+
STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
909+
STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
910+
STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
911+
STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
912+
STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
913+
STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
914+
STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
915+
STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
916+
STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
917+
STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
918+
STM32_GATE_CFG(TSC, tsc, SECF_TZC),
919+
STM32_GATE_CFG(PKA, pka, SECF_PKA),
920+
STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
921+
STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
922+
STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
923+
STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
924+
STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
925+
STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
926+
STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
927+
STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
928+
STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
929+
STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
930+
STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
931+
STM32_GATE_CFG(USBH, usbh, SECF_NONE),
932+
STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
933+
STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
934+
STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
935+
576936
STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
577937
STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
578938
STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),

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