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arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports
Add device nodes and connections to support USB 3.x on the SoC's integrated USBi Type-C ports of M2-based devices. Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x controller, two DART iommu instances and a CD321x USB PD controller. The port labels use Apple's established naming scheme for the ports. Signed-off-by: Hector Martin <marcan@marcan.st> Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Sven Peter <sven@kernel.org> # M1 mac mini and macbook air Reviewed-by: Sven Peter <sven@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-2-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter <sven@kernel.org>
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‎arch/arm64/boot/dts/apple/t8112-j413.dts‎

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};
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};
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/*
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* Provide labels for the USB type C ports.
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*/
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&typec0 {
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label = "USB-C Left-back";
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};
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&typec1 {
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label = "USB-C Left-front";
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};
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&i2c0 {
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/* MagSafe port */
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hpm5: usb-pd@3a {

‎arch/arm64/boot/dts/apple/t8112-j415.dts‎

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};
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};
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/*
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* Provide labels for the USB type C ports.
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*/
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&typec0 {
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label = "USB-C Left-back";
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};
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&typec1 {
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label = "USB-C Left-front";
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};
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&i2c0 {
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/* MagSafe port */
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hpm5: usb-pd@3a {

‎arch/arm64/boot/dts/apple/t8112-j473.dts‎

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&pcie2_dart {
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status = "okay";
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};
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/*
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* Provide labels for the USB type C ports.
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*/
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&typec0 {
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label = "USB-C Back-left";
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};
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&typec1 {
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label = "USB-C Back-right";
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};

‎arch/arm64/boot/dts/apple/t8112-j493.dts‎

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@@ -108,6 +108,18 @@
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};
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};
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/*
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* Provide labels for the USB type C ports.
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*/
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&typec0 {
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label = "USB-C Left-back";
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};
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&typec1 {
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label = "USB-C Left-front";
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};
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111123
&i2c4 {
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status = "okay";
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};

‎arch/arm64/boot/dts/apple/t8112-jxxx.dtsi‎

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/ {
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aliases {
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atcphy0 = &atcphy0;
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atcphy1 = &atcphy1;
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serial0 = &serial0;
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serial2 = &serial2;
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};
@@ -53,6 +55,29 @@
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interrupt-parent = <&pinctrl_ap>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "irq";
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typec0: connector {
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compatible = "usb-c-connector";
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power-role = "dual";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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typec0_connector_hs: endpoint {
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remote-endpoint = <&dwc3_0_hs>;
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};
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};
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port@1 {
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reg = <1>;
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typec0_connector_ss: endpoint {
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remote-endpoint = <&atcphy0_typec_lanes>;
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};
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};
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};
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};
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};
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hpm1: usb-pd@3f {
@@ -61,6 +86,115 @@
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interrupt-parent = <&pinctrl_ap>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "irq";
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typec1: connector {
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compatible = "usb-c-connector";
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power-role = "dual";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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typec1_connector_hs: endpoint {
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remote-endpoint = <&dwc3_1_hs>;
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};
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};
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port@1 {
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reg = <1>;
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typec1_connector_ss: endpoint {
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remote-endpoint = <&atcphy1_typec_lanes>;
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};
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};
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};
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};
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};
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};
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/* USB controllers */
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&dwc3_0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dwc3_0_hs: endpoint {
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remote-endpoint = <&typec0_connector_hs>;
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};
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};
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port@1 {
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reg = <1>;
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dwc3_0_ss: endpoint {
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remote-endpoint = <&atcphy0_usb3>;
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};
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};
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};
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};
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&dwc3_1 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dwc3_1_hs: endpoint {
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remote-endpoint = <&typec1_connector_hs>;
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};
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};
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port@1 {
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reg = <1>;
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dwc3_1_ss: endpoint {
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remote-endpoint = <&atcphy1_usb3>;
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};
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};
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};
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};
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/* Type-C PHYs */
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&atcphy0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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atcphy0_typec_lanes: endpoint {
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remote-endpoint = <&typec0_connector_ss>;
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};
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};
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port@1 {
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reg = <1>;
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atcphy0_usb3: endpoint {
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remote-endpoint = <&dwc3_0_ss>;
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};
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};
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};
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};
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&atcphy1 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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atcphy1_typec_lanes: endpoint {
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remote-endpoint = <&typec1_connector_ss>;
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};
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};
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port@1 {
193+
reg = <1>;
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atcphy1_usb3: endpoint {
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remote-endpoint = <&dwc3_1_ss>;
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};
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};
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};
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};
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‎arch/arm64/boot/dts/apple/t8112.dtsi‎

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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/spmi/spmi.h>
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/ {
@@ -1010,6 +1011,110 @@
10101011
resets = <&ps_ans>;
10111012
};
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dwc3_0: usb@382280000 {
1015+
compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
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reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>;
1017+
reg-names = "dwc3-core", "dwc3-apple";
1018+
interrupt-parent = <&aic>;
1019+
interrupts = <AIC_IRQ 1031 IRQ_TYPE_LEVEL_HIGH>;
1020+
dr_mode = "otg";
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usb-role-switch;
1022+
role-switch-default-mode = "host";
1023+
iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
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power-domains = <&ps_atc0_usb>;
1025+
resets = <&atcphy0>;
1026+
phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>;
1027+
phy-names = "usb2-phy", "usb3-phy";
1028+
};
1029+
1030+
dwc3_0_dart_0: iommu@382f00000 {
1031+
compatible = "apple,t8110-dart";
1032+
reg = <0x3 0x82f00000 0x0 0x4000>;
1033+
interrupt-parent = <&aic>;
1034+
interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
1035+
#iommu-cells = <1>;
1036+
power-domains = <&ps_atc0_usb>;
1037+
};
1038+
1039+
dwc3_0_dart_1: iommu@382f80000 {
1040+
compatible = "apple,t8110-dart";
1041+
reg = <0x3 0x82f80000 0x0 0x4000>;
1042+
interrupt-parent = <&aic>;
1043+
interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
1044+
#iommu-cells = <1>;
1045+
power-domains = <&ps_atc0_usb>;
1046+
};
1047+
1048+
atcphy0: phy@383000000 {
1049+
compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
1050+
reg = <0x3 0x83000000 0x0 0x4c000>,
1051+
<0x3 0x83050000 0x0 0x8000>,
1052+
<0x3 0x80000000 0x0 0x4000>,
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<0x3 0x82a90000 0x0 0x4000>,
1054+
<0x3 0x82a84000 0x0 0x4000>;
1055+
reg-names = "core", "lpdptx", "axi2af", "usb2phy",
1056+
"pipehandler";
1057+
1058+
#phy-cells = <1>;
1059+
#reset-cells = <0>;
1060+
1061+
orientation-switch;
1062+
mode-switch;
1063+
power-domains = <&ps_atc0_usb>;
1064+
};
1065+
1066+
dwc3_1: usb@502280000 {
1067+
compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
1068+
reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>;
1069+
reg-names = "dwc3-core", "dwc3-apple";
1070+
interrupt-parent = <&aic>;
1071+
interrupts = <AIC_IRQ 1112 IRQ_TYPE_LEVEL_HIGH>;
1072+
dr_mode = "otg";
1073+
usb-role-switch;
1074+
role-switch-default-mode = "host";
1075+
iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
1076+
power-domains = <&ps_atc1_usb>;
1077+
resets = <&atcphy1>;
1078+
phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>;
1079+
phy-names = "usb2-phy", "usb3-phy";
1080+
};
1081+
1082+
dwc3_1_dart_0: iommu@502f00000 {
1083+
compatible = "apple,t8110-dart";
1084+
reg = <0x5 0x02f00000 0x0 0x4000>;
1085+
interrupt-parent = <&aic>;
1086+
interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
1087+
#iommu-cells = <1>;
1088+
power-domains = <&ps_atc1_usb>;
1089+
};
1090+
1091+
dwc3_1_dart_1: iommu@502f80000 {
1092+
compatible = "apple,t8110-dart";
1093+
reg = <0x5 0x02f80000 0x0 0x4000>;
1094+
interrupt-parent = <&aic>;
1095+
interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
1096+
#iommu-cells = <1>;
1097+
power-domains = <&ps_atc1_usb>;
1098+
};
1099+
1100+
atcphy1: phy@503000000 {
1101+
compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
1102+
reg = <0x5 0x03000000 0x0 0x4c000>,
1103+
<0x5 0x03050000 0x0 0x8000>,
1104+
<0x5 0x0 0x0 0x4000>,
1105+
<0x5 0x02a90000 0x0 0x4000>,
1106+
<0x5 0x02a84000 0x0 0x4000>;
1107+
reg-names = "core", "lpdptx", "axi2af", "usb2phy",
1108+
"pipehandler";
1109+
1110+
#phy-cells = <1>;
1111+
#reset-cells = <0>;
1112+
1113+
orientation-switch;
1114+
mode-switch;
1115+
power-domains = <&ps_atc1_usb>;
1116+
};
1117+
10131118
pcie0_dart: iommu@681008000 {
10141119
compatible = "apple,t8110-dart";
10151120
reg = <0x6 0x81008000 0x0 0x4000>;

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