Skip to content

Commit bc3c566

Browse files
victorlu-amdalexdeucher
victorlu-amd
authored and
alexdeucher
committed
drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)
WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait are not using the correct rlcg interface or mec engine, respectively. Add xcc instance parameter to them. v4: Use GET_INST and squash commit with: "drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait" v3: xcc not needed for MMMHUB v2: rebase Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent f64c3fc commit bc3c566

6 files changed

Lines changed: 25 additions & 19 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,9 +73,10 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
7373

7474
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
7575
uint32_t reg0, uint32_t reg1,
76-
uint32_t ref, uint32_t mask)
76+
uint32_t ref, uint32_t mask,
77+
uint32_t xcc_inst)
7778
{
78-
struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
79+
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst];
7980
struct amdgpu_ring *ring = &kiq->ring;
8081
signed long r, cnt = 0;
8182
unsigned long flags;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
334334
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
335335
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
336336
uint32_t reg0, uint32_t rreg1,
337-
uint32_t ref, uint32_t mask);
337+
uint32_t ref, uint32_t mask,
338+
uint32_t xcc_inst);
338339
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
339340
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
340341
int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);

‎drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
268268
if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
269269
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
270270
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
271-
1 << vmid);
271+
1 << vmid, GET_INST(GC, 0));
272272
return;
273273
}
274274

‎drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
229229
if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
230230
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
231231
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
232-
1 << vmid);
232+
1 << vmid, GET_INST(GC, 0));
233233
return;
234234
}
235235

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c‎

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -817,7 +817,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
817817
uint32_t vmhub, uint32_t flush_type)
818818
{
819819
bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
820-
u32 j, inv_req, tmp, sem, req, ack;
820+
u32 j, inv_req, tmp, sem, req, ack, inst;
821821
const unsigned int eng = 17;
822822
struct amdgpu_vmhub *hub;
823823

@@ -832,13 +832,17 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
832832
/* This is necessary for a HW workaround under SRIOV as well
833833
* as GFXOFF under bare metal
834834
*/
835-
if (adev->gfx.kiq[0].ring.sched.ready &&
835+
if (vmhub >= AMDGPU_MMHUB0(0))
836+
inst = GET_INST(GC, 0);
837+
else
838+
inst = vmhub;
839+
if (adev->gfx.kiq[inst].ring.sched.ready &&
836840
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
837841
uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
838842
uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
839843

840844
amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
841-
1 << vmid);
845+
1 << vmid, inst);
842846
return;
843847
}
844848

@@ -856,9 +860,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
856860
for (j = 0; j < adev->usec_timeout; j++) {
857861
/* a read return value of 1 means semaphore acquire */
858862
if (vmhub >= AMDGPU_MMHUB0(0))
859-
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem);
863+
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst);
860864
else
861-
tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem);
865+
tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst);
862866
if (tmp & 0x1)
863867
break;
864868
udelay(1);
@@ -869,9 +873,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
869873
}
870874

871875
if (vmhub >= AMDGPU_MMHUB0(0))
872-
WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req);
876+
WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst);
873877
else
874-
WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req);
878+
WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst);
875879

876880
/*
877881
* Issue a dummy read to wait for the ACK register to
@@ -884,9 +888,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
884888

885889
for (j = 0; j < adev->usec_timeout; j++) {
886890
if (vmhub >= AMDGPU_MMHUB0(0))
887-
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack);
891+
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst);
888892
else
889-
tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack);
893+
tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst);
890894
if (tmp & (1 << vmid))
891895
break;
892896
udelay(1);
@@ -899,9 +903,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
899903
* write with 0 means semaphore release
900904
*/
901905
if (vmhub >= AMDGPU_MMHUB0(0))
902-
WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0);
906+
WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst);
903907
else
904-
WREG32_SOC15_IP_NO_KIQ(GC, sem, 0);
908+
WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst);
905909
}
906910

907911
spin_unlock(&adev->gmc.invalidate_lock);

‎drivers/gpu/drm/amd/amdgpu/soc15_common.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969

7070
#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)
7171

72-
#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
72+
#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
7373

7474
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
7575
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
@@ -86,8 +86,8 @@
8686
#define WREG32_SOC15_IP(ip, reg, value) \
8787
__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
8888

89-
#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
90-
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
89+
#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
90+
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
9191

9292
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
9393
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \

0 commit comments

Comments
 (0)