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phy: qcom: qmp: move common bits definitions to common header
Move bit definitions for the common headers to the common phy-qcom-qmp.h header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent ef643d5 commit c01e03f

8 files changed

Lines changed: 26 additions & 137 deletions

‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c‎

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@@ -41,16 +41,6 @@
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#include "phy-qcom-qmp-dp-phy-v5.h"
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#include "phy-qcom-qmp-dp-phy-v6.h"
4343

44-
/* QPHY_SW_RESET bit */
45-
#define SW_RESET BIT(0)
46-
/* QPHY_POWER_DOWN_CONTROL */
47-
#define SW_PWRDN BIT(0)
48-
/* QPHY_START_CONTROL bits */
49-
#define SERDES_START BIT(0)
50-
#define PCS_START BIT(1)
51-
/* QPHY_PCS_STATUS bit */
52-
#define PHYSTATUS BIT(6)
53-
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/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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/* DP PHY soft reset */
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#define SW_DPPHY_RESET BIT(0)
@@ -65,17 +55,6 @@
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#define USB3_MODE BIT(0) /* enables USB3 mode */
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#define DP_MODE BIT(1) /* enables DP mode */
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68-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
69-
#define ARCVR_DTCT_EN BIT(0)
70-
#define ALFPS_DTCT_EN BIT(1)
71-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
72-
73-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
74-
#define IRQ_CLEAR BIT(0)
75-
76-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
77-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
78-
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/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
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#define SW_PORTSELECT_VAL BIT(0)
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#define SW_PORTSELECT_MUX BIT(1)

‎drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c‎

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@@ -23,17 +23,9 @@
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#include "phy-qcom-qmp.h"
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26-
/* QPHY_SW_RESET bit */
27-
#define SW_RESET BIT(0)
28-
/* QPHY_POWER_DOWN_CONTROL */
29-
#define SW_PWRDN BIT(0)
30-
#define REFCLK_DRV_DSBL BIT(1)
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/* QPHY_START_CONTROL bits */
32-
#define SERDES_START BIT(0)
33-
#define PCS_START BIT(1)
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#define PLL_READY_GATE_EN BIT(3)
35-
/* QPHY_PCS_STATUS bit */
36-
#define PHYSTATUS BIT(6)
28+
3729
/* QPHY_COM_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

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@@ -34,18 +34,6 @@
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#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
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#include "phy-qcom-qmp-pcie-qhp.h"
3636

37-
/* QPHY_SW_RESET bit */
38-
#define SW_RESET BIT(0)
39-
/* QPHY_POWER_DOWN_CONTROL */
40-
#define SW_PWRDN BIT(0)
41-
#define REFCLK_DRV_DSBL BIT(1)
42-
/* QPHY_START_CONTROL bits */
43-
#define SERDES_START BIT(0)
44-
#define PCS_START BIT(1)
45-
/* QPHY_PCS_STATUS bit */
46-
#define PHYSTATUS BIT(6)
47-
#define PHYSTATUS_4_20 BIT(7)
48-
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#define PHY_INIT_COMPLETE_TIMEOUT 10000
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/* set of registers with offsets different per-PHY */

‎drivers/phy/qualcomm/phy-qcom-qmp-ufs.c‎

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Original file line numberDiff line numberDiff line change
@@ -32,13 +32,6 @@
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#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
3434

35-
/* QPHY_SW_RESET bit */
36-
#define SW_RESET BIT(0)
37-
/* QPHY_POWER_DOWN_CONTROL */
38-
#define SW_PWRDN BIT(0)
39-
/* QPHY_START_CONTROL bits */
40-
#define SERDES_START BIT(0)
41-
#define PCS_START BIT(1)
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/* QPHY_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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‎drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c‎

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@@ -27,16 +27,6 @@
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#include "phy-qcom-qmp-dp-com-v3.h"
2929

30-
/* QPHY_SW_RESET bit */
31-
#define SW_RESET BIT(0)
32-
/* QPHY_POWER_DOWN_CONTROL */
33-
#define SW_PWRDN BIT(0)
34-
/* QPHY_START_CONTROL bits */
35-
#define SERDES_START BIT(0)
36-
#define PCS_START BIT(1)
37-
/* QPHY_PCS_STATUS bit */
38-
#define PHYSTATUS BIT(6)
39-
4030
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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/* DP PHY soft reset */
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#define SW_DPPHY_RESET BIT(0)
@@ -51,17 +41,6 @@
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#define USB3_MODE BIT(0) /* enables USB3 mode */
5242
#define DP_MODE BIT(1) /* enables DP mode */
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54-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
55-
#define ARCVR_DTCT_EN BIT(0)
56-
#define ALFPS_DTCT_EN BIT(1)
57-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
58-
59-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
60-
#define IRQ_CLEAR BIT(0)
61-
62-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
64-
6544
#define PHY_INIT_COMPLETE_TIMEOUT 10000
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6746
struct qmp_phy_init_tbl {

‎drivers/phy/qualcomm/phy-qcom-qmp-usb.c‎

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Original file line numberDiff line numberDiff line change
@@ -29,41 +29,6 @@
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#include "phy-qcom-qmp-pcs-usb-v6.h"
3030
#include "phy-qcom-qmp-pcs-usb-v7.h"
3131

32-
/* QPHY_SW_RESET bit */
33-
#define SW_RESET BIT(0)
34-
/* QPHY_POWER_DOWN_CONTROL */
35-
#define SW_PWRDN BIT(0)
36-
/* QPHY_START_CONTROL bits */
37-
#define SERDES_START BIT(0)
38-
#define PCS_START BIT(1)
39-
/* QPHY_PCS_STATUS bit */
40-
#define PHYSTATUS BIT(6)
41-
42-
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
43-
/* DP PHY soft reset */
44-
#define SW_DPPHY_RESET BIT(0)
45-
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46-
#define SW_DPPHY_RESET_MUX BIT(1)
47-
/* USB3 PHY soft reset */
48-
#define SW_USB3PHY_RESET BIT(2)
49-
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
50-
#define SW_USB3PHY_RESET_MUX BIT(3)
51-
52-
/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
53-
#define USB3_MODE BIT(0) /* enables USB3 mode */
54-
#define DP_MODE BIT(1) /* enables DP mode */
55-
56-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
57-
#define ARCVR_DTCT_EN BIT(0)
58-
#define ALFPS_DTCT_EN BIT(1)
59-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
60-
61-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
62-
#define IRQ_CLEAR BIT(0)
63-
64-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
65-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
66-
6732
#define PHY_INIT_COMPLETE_TIMEOUT 10000
6833

6934
/* set of registers with offsets different per-PHY */

‎drivers/phy/qualcomm/phy-qcom-qmp-usbc.c‎

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@@ -28,38 +28,6 @@
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#include "phy-qcom-qmp.h"
2929
#include "phy-qcom-qmp-pcs-misc-v3.h"
3030

31-
/* QPHY_SW_RESET bit */
32-
#define SW_RESET BIT(0)
33-
/* QPHY_POWER_DOWN_CONTROL */
34-
#define SW_PWRDN BIT(0)
35-
/* QPHY_START_CONTROL bits */
36-
#define SERDES_START BIT(0)
37-
#define PCS_START BIT(1)
38-
/* QPHY_PCS_STATUS bit */
39-
#define PHYSTATUS BIT(6)
40-
41-
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
42-
/* DP PHY soft reset */
43-
#define SW_DPPHY_RESET BIT(0)
44-
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
45-
#define SW_DPPHY_RESET_MUX BIT(1)
46-
/* USB3 PHY soft reset */
47-
#define SW_USB3PHY_RESET BIT(2)
48-
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49-
#define SW_USB3PHY_RESET_MUX BIT(3)
50-
51-
/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
52-
#define USB3_MODE BIT(0) /* enables USB3 mode */
53-
#define DP_MODE BIT(1) /* enables DP mode */
54-
55-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
56-
#define ARCVR_DTCT_EN BIT(0)
57-
#define ALFPS_DTCT_EN BIT(1)
58-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
59-
60-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61-
#define IRQ_CLEAR BIT(0)
62-
6331
#define PHY_INIT_COMPLETE_TIMEOUT 10000
6432

6533
/* set of registers with offsets different per-PHY */

‎drivers/phy/qualcomm/phy-qcom-qmp.h‎

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@@ -50,4 +50,29 @@
5050

5151
#include "phy-qcom-qmp-pcs-v7.h"
5252

53+
/* QPHY_SW_RESET bit */
54+
#define SW_RESET BIT(0)
55+
/* QPHY_POWER_DOWN_CONTROL */
56+
#define SW_PWRDN BIT(0)
57+
#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
58+
59+
/* QPHY_START_CONTROL bits */
60+
#define SERDES_START BIT(0)
61+
#define PCS_START BIT(1)
62+
63+
/* QPHY_PCS_STATUS bit */
64+
#define PHYSTATUS BIT(6)
65+
#define PHYSTATUS_4_20 BIT(7)
66+
67+
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
68+
#define ARCVR_DTCT_EN BIT(0)
69+
#define ALFPS_DTCT_EN BIT(1)
70+
#define ARCVR_DTCT_EVENT_SEL BIT(4)
71+
72+
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
73+
#define IRQ_CLEAR BIT(0)
74+
75+
/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
76+
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
77+
5378
#endif

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