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phy: qcom: qmp: split DP PHY registers to separate headers
Split the DP PHY register definitions to separate headers, removing them from the global one. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-4-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent 53d7776 commit ef643d5

10 files changed

Lines changed: 159 additions & 90 deletions

‎drivers/phy/qualcomm/phy-qcom-edp.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,8 @@
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#include <dt-bindings/phy/phy.h>
2323

24-
#include "phy-qcom-qmp.h"
24+
#include "phy-qcom-qmp-dp-phy.h"
25+
#include "phy-qcom-qmp-qserdes-com-v4.h"
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/* EDP_PHY registers */
2728
#define DP_PHY_CFG 0x0010

‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,14 @@
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#include "phy-qcom-qmp-pcs-usb-v5.h"
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#include "phy-qcom-qmp-pcs-usb-v6.h"
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36+
#include "phy-qcom-qmp-dp-com-v3.h"
37+
38+
#include "phy-qcom-qmp-dp-phy.h"
39+
#include "phy-qcom-qmp-dp-phy-v3.h"
40+
#include "phy-qcom-qmp-dp-phy-v4.h"
41+
#include "phy-qcom-qmp-dp-phy-v5.h"
42+
#include "phy-qcom-qmp-dp-phy-v6.h"
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3644
/* QPHY_SW_RESET bit */
3745
#define SW_RESET BIT(0)
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/* QPHY_POWER_DOWN_CONTROL */
@@ -2322,7 +2330,7 @@ static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
23222330
u32 status;
23232331
int ret;
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2325-
writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
2333+
writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
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23272335
qmp_combo_configure_dp_mode(qmp);
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‎drivers/phy/qualcomm/phy-qcom-qmp-dp-com-v3.h‎

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@@ -0,0 +1,18 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
5+
6+
#ifndef QCOM_PHY_QMP_DP_COM_V3_H_
7+
#define QCOM_PHY_QMP_DP_COM_V3_H_
8+
9+
/* Only for QMP V3 & V4 PHY - DP COM registers */
10+
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
11+
#define QPHY_V3_DP_COM_SW_RESET 0x04
12+
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
13+
#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
14+
#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
15+
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
16+
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
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18+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v3.h‎

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@@ -0,0 +1,21 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
3+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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6+
#ifndef QCOM_PHY_QMP_DP_PHY_V3_H_
7+
#define QCOM_PHY_QMP_DP_PHY_V3_H_
8+
9+
/* Only for QMP V3 PHY - DP PHY registers */
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#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
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#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
12+
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
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14+
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
15+
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
16+
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
17+
18+
#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
19+
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
20+
21+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v4.h‎

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@@ -0,0 +1,19 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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6+
#ifndef QCOM_PHY_QMP_DP_PHY_V4_H_
7+
#define QCOM_PHY_QMP_DP_PHY_V4_H_
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9+
/* Only for QMP V4 PHY - DP PHY registers */
10+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
11+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
12+
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
13+
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
14+
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
15+
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
16+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
17+
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
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19+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v5.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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6+
#ifndef QCOM_PHY_QMP_DP_PHY_V5_H_
7+
#define QCOM_PHY_QMP_DP_PHY_V5_H_
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9+
/* Only for QMP V5 PHY - DP PHY registers */
10+
#define QSERDES_V5_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
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#define QSERDES_V5_DP_PHY_STATUS 0x0dc
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13+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v6.h‎

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1+
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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6+
#ifndef QCOM_PHY_QMP_DP_PHY_V6_H_
7+
#define QCOM_PHY_QMP_DP_PHY_V6_H_
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9+
/* Only for QMP V6 PHY - DP PHY registers */
10+
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
11+
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
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13+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_DP_PHY_H_
7+
#define QCOM_PHY_QMP_DP_PHY_H_
8+
9+
/* QMP PHY - DP PHY registers */
10+
#define QSERDES_DP_PHY_REVISION_ID0 0x000
11+
#define QSERDES_DP_PHY_REVISION_ID1 0x004
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#define QSERDES_DP_PHY_REVISION_ID2 0x008
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#define QSERDES_DP_PHY_REVISION_ID3 0x00c
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#define QSERDES_DP_PHY_CFG 0x010
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#define QSERDES_DP_PHY_CFG_1 0x014
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#define QSERDES_DP_PHY_PD_CTL 0x018
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#define QSERDES_DP_PHY_MODE 0x01c
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#define QSERDES_DP_PHY_AUX_CFG0 0x020
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#define QSERDES_DP_PHY_AUX_CFG1 0x024
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#define QSERDES_DP_PHY_AUX_CFG2 0x028
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#define QSERDES_DP_PHY_AUX_CFG3 0x02c
22+
#define QSERDES_DP_PHY_AUX_CFG4 0x030
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#define QSERDES_DP_PHY_AUX_CFG5 0x034
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#define QSERDES_DP_PHY_AUX_CFG6 0x038
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#define QSERDES_DP_PHY_AUX_CFG7 0x03c
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#define QSERDES_DP_PHY_AUX_CFG8 0x040
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#define QSERDES_DP_PHY_AUX_CFG9 0x044
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29+
/* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */
30+
# define QSERDES_V3_COM_BIAS_EN 0x0001
31+
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
32+
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
33+
# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
34+
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
35+
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
36+
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
37+
38+
/* QPHY_TX_TX_EMP_POST1_LVL bits */
39+
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
40+
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
41+
42+
/* QPHY_TX_TX_DRV_LVL bits */
43+
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
44+
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
45+
46+
/* QSERDES_DP_PHY_PD_CTL bits */
47+
# define DP_PHY_PD_CTL_PWRDN 0x001
48+
# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
49+
# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
50+
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
51+
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
52+
# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
53+
# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
54+
55+
/* QPHY_DP_PHY_AUX_INTERRUPT_STATUS bits */
56+
# define PHY_AUX_STOP_ERR_MASK 0x01
57+
# define PHY_AUX_DEC_ERR_MASK 0x02
58+
# define PHY_AUX_SYNC_ERR_MASK 0x04
59+
# define PHY_AUX_ALIGN_ERR_MASK 0x08
60+
# define PHY_AUX_REQ_ERR_MASK 0x10
61+
62+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c‎

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Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
2525
#include "phy-qcom-qmp-pcs-usb-v4.h"
2626
#include "phy-qcom-qmp-pcs-usb-v5.h"
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28+
#include "phy-qcom-qmp-dp-com-v3.h"
29+
2830
/* QPHY_SW_RESET bit */
2931
#define SW_RESET BIT(0)
3032
/* QPHY_POWER_DOWN_CONTROL */

‎drivers/phy/qualcomm/phy-qcom-qmp.h‎

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Original file line numberDiff line numberDiff line change
@@ -50,92 +50,4 @@
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5151
#include "phy-qcom-qmp-pcs-v7.h"
5252

53-
/* Only for QMP V3 & V4 PHY - DP COM registers */
54-
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
55-
#define QPHY_V3_DP_COM_SW_RESET 0x04
56-
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
57-
#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
58-
#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
59-
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
60-
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
61-
62-
/* QSERDES V3 COM bits */
63-
# define QSERDES_V3_COM_BIAS_EN 0x0001
64-
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
65-
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
66-
# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
67-
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
68-
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
69-
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
70-
71-
/* QSERDES V3 TX bits */
72-
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
73-
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
74-
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
75-
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
76-
77-
/* QMP PHY - DP PHY registers */
78-
#define QSERDES_DP_PHY_REVISION_ID0 0x000
79-
#define QSERDES_DP_PHY_REVISION_ID1 0x004
80-
#define QSERDES_DP_PHY_REVISION_ID2 0x008
81-
#define QSERDES_DP_PHY_REVISION_ID3 0x00c
82-
#define QSERDES_DP_PHY_CFG 0x010
83-
#define QSERDES_DP_PHY_PD_CTL 0x018
84-
# define DP_PHY_PD_CTL_PWRDN 0x001
85-
# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
86-
# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
87-
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
88-
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
89-
# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
90-
# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
91-
#define QSERDES_DP_PHY_MODE 0x01c
92-
#define QSERDES_DP_PHY_AUX_CFG0 0x020
93-
#define QSERDES_DP_PHY_AUX_CFG1 0x024
94-
#define QSERDES_DP_PHY_AUX_CFG2 0x028
95-
#define QSERDES_DP_PHY_AUX_CFG3 0x02c
96-
#define QSERDES_DP_PHY_AUX_CFG4 0x030
97-
#define QSERDES_DP_PHY_AUX_CFG5 0x034
98-
#define QSERDES_DP_PHY_AUX_CFG6 0x038
99-
#define QSERDES_DP_PHY_AUX_CFG7 0x03c
100-
#define QSERDES_DP_PHY_AUX_CFG8 0x040
101-
#define QSERDES_DP_PHY_AUX_CFG9 0x044
102-
103-
/* Only for QMP V3 PHY - DP PHY registers */
104-
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
105-
# define PHY_AUX_STOP_ERR_MASK 0x01
106-
# define PHY_AUX_DEC_ERR_MASK 0x02
107-
# define PHY_AUX_SYNC_ERR_MASK 0x04
108-
# define PHY_AUX_ALIGN_ERR_MASK 0x08
109-
# define PHY_AUX_REQ_ERR_MASK 0x10
110-
111-
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
112-
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
113-
114-
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
115-
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
116-
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
117-
118-
#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
119-
#define DP_PHY_SPARE0_MASK 0x0f
120-
#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
121-
122-
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
123-
124-
/* Only for QMP V4 PHY - DP PHY registers */
125-
#define QSERDES_V4_DP_PHY_CFG_1 0x014
126-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
127-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
128-
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
129-
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
130-
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
131-
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
132-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
133-
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
134-
135-
#define QSERDES_V5_DP_PHY_STATUS 0x0dc
136-
137-
/* Only for QMP V6 PHY - DP PHY registers */
138-
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
139-
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
140-
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#endif

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