Skip to content

Commit c5dc31b

Browse files
arndbarndb
committed
Merge branch 'bst/newsoc' into soc/newsoc
This patch series introduces platform support for Black Sesame Technologies (BST) C1200 SoC and CDCU1.0 ADAS 4C2G board. BST is a leading automotive-grade computing SoC provider focusing on intelligent driving, computer vision, and AI capabilities for ADAS and autonomous driving applications. You can find more information about the SoC and related boards at: https://bst.ai This series provides the foundational platform enablement including device tree bindings, SoC and board device trees, platform configuration, and maintainer information. MMC/SDHCI driver support will be submitted in a separate patch series. * bst/newsoc: MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support arm64: defconfig: enable BST platform support arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs dt-bindings: arm: add Black Sesame Technologies (bst) SoC dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. Link: https://lore.kernel.org/all/20251016120558.2390960-1-yangzh0906@thundersoft.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 2bab992 + 92bcb8c commit c5dc31b

9 files changed

Lines changed: 174 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/arm/bst.yaml‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/arm/bst.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: BST platforms
8+
9+
description:
10+
Black Sesame Technologies (BST) is a semiconductor company that produces
11+
automotive-grade system-on-chips (SoCs) for intelligent driving, focusing
12+
on computer vision and AI capabilities. The BST C1200 family includes SoCs
13+
for ADAS (Advanced Driver Assistance Systems) and autonomous driving
14+
applications.
15+
16+
maintainers:
17+
- Ge Gordon <gordon.ge@bst.ai>
18+
19+
properties:
20+
$nodename:
21+
const: '/'
22+
compatible:
23+
oneOf:
24+
- description: BST C1200 CDCU1.0 ADAS 4C2G board
25+
items:
26+
- const: bst,c1200-cdcu1.0-adas-4c2g
27+
- const: bst,c1200
28+
29+
additionalProperties: true
30+
31+
...

‎Documentation/devicetree/bindings/vendor-prefixes.yaml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,8 @@ patternProperties:
251251
description: Shanghai Broadmobi Communication Technology Co.,Ltd.
252252
"^bsh,.*":
253253
description: BSH Hausgeraete GmbH
254+
"^bst,.*":
255+
description: Black Sesame Technologies Co., Ltd.
254256
"^bticino,.*":
255257
description: Bticino International
256258
"^buffalo,.*":

‎MAINTAINERS‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2547,6 +2547,14 @@ S: Maintained
25472547
F: Documentation/devicetree/bindings/arm/blaize.yaml
25482548
F: arch/arm64/boot/dts/blaize/
25492549

2550+
ARM/BST SOC SUPPORT
2551+
M: Ge Gordon <gordon.ge@bst.ai>
2552+
R: BST Linux Kernel Upstream Group <bst-upstream@bstai.top>
2553+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2554+
S: Supported
2555+
F: Documentation/devicetree/bindings/arm/bst.yaml
2556+
F: arch/arm64/boot/dts/bst/
2557+
25502558
ARM/CALXEDA HIGHBANK ARCHITECTURE
25512559
M: Andre Przywara <andre.przywara@arm.com>
25522560
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

‎arch/arm64/Kconfig.platforms‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,14 @@ config ARCH_BLAIZE
119119
help
120120
This enables support for the Blaize SoC family
121121

122+
config ARCH_BST
123+
bool "Black Sesame Technologies SoC Family"
124+
help
125+
This enables support for Black Sesame Technologies (BST) SoC family.
126+
BST produces automotive-grade system-on-chips for intelligent driving,
127+
focusing on computer vision and AI capabilities. The BST C1200 family
128+
includes SoCs for ADAS and autonomous driving applications.
129+
122130
config ARCH_CIX
123131
bool "Cixtech SoC family"
124132
help

‎arch/arm64/boot/dts/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ subdir-y += axiado
1313
subdir-y += bitmain
1414
subdir-y += blaize
1515
subdir-y += broadcom
16+
subdir-y += bst
1617
subdir-y += cavium
1718
subdir-y += cix
1819
subdir-y += exynos

‎arch/arm64/boot/dts/bst/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb

‎arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/dts-v1/;
3+
4+
#include "bstc1200.dtsi"
5+
6+
/ {
7+
model = "BST C1200-96 CDCU1.0 4C2G";
8+
compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
9+
10+
chosen {
11+
stdout-path = "serial0:115200n8";
12+
};
13+
14+
memory@810000000 {
15+
device_type = "memory";
16+
reg = <0x8 0x10000000 0x0 0x30000000>,
17+
<0x8 0xc0000000 0x1 0x0>,
18+
<0xc 0x00000000 0x0 0x40000000>;
19+
};
20+
};
21+
22+
&uart0 {
23+
status = "okay";
24+
};

‎arch/arm64/boot/dts/bst/bstc1200.dtsi‎

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,97 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
#include <dt-bindings/interrupt-controller/arm-gic.h>
3+
#include <dt-bindings/interrupt-controller/irq.h>
4+
5+
/ {
6+
compatible = "bst,c1200";
7+
#address-cells = <2>;
8+
#size-cells = <2>;
9+
10+
cpus {
11+
#address-cells = <1>;
12+
#size-cells = <0>;
13+
14+
cpu@0 {
15+
device_type = "cpu";
16+
compatible = "arm,cortex-a78";
17+
reg = <0x0>;
18+
enable-method = "psci";
19+
next-level-cache = <&l2_cache>;
20+
};
21+
22+
cpu@1 {
23+
device_type = "cpu";
24+
compatible = "arm,cortex-a78";
25+
reg = <0x100>;
26+
enable-method = "psci";
27+
next-level-cache = <&l2_cache>;
28+
};
29+
30+
cpu@2 {
31+
device_type = "cpu";
32+
compatible = "arm,cortex-a78";
33+
reg = <0x200>;
34+
enable-method = "psci";
35+
next-level-cache = <&l2_cache>;
36+
};
37+
38+
cpu@3 {
39+
device_type = "cpu";
40+
compatible = "arm,cortex-a78";
41+
reg = <0x300>;
42+
enable-method = "psci";
43+
next-level-cache = <&l2_cache>;
44+
};
45+
46+
l2_cache: l2-cache {
47+
compatible = "cache";
48+
cache-level = <2>;
49+
cache-unified;
50+
};
51+
};
52+
53+
psci {
54+
compatible = "arm,psci-1.0";
55+
method = "smc";
56+
};
57+
58+
soc {
59+
compatible = "simple-bus";
60+
ranges;
61+
#address-cells = <2>;
62+
#size-cells = <2>;
63+
interrupt-parent = <&gic>;
64+
65+
uart0: serial@20008000 {
66+
compatible = "snps,dw-apb-uart";
67+
reg = <0x0 0x20008000 0x0 0x1000>;
68+
clock-frequency = <25000000>;
69+
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
70+
reg-shift = <2>;
71+
reg-io-width = <4>;
72+
status = "disabled";
73+
};
74+
75+
gic: interrupt-controller@32800000 {
76+
compatible = "arm,gic-v3";
77+
reg = <0x0 0x32800000 0x0 0x10000>,
78+
<0x0 0x32880000 0x0 0x100000>;
79+
ranges;
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
#interrupt-cells = <3>;
83+
interrupt-controller;
84+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
85+
};
86+
};
87+
88+
timer {
89+
compatible = "arm,armv8-timer";
90+
always-on;
91+
interrupt-parent = <&gic>;
92+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
93+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
94+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
95+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
96+
};
97+
};

‎arch/arm64/configs/defconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ CONFIG_ARCH_BCMBCA=y
4747
CONFIG_ARCH_BRCMSTB=y
4848
CONFIG_ARCH_BERLIN=y
4949
CONFIG_ARCH_BLAIZE=y
50+
CONFIG_ARCH_BST=y
5051
CONFIG_ARCH_CIX=y
5152
CONFIG_ARCH_EXYNOS=y
5253
CONFIG_ARCH_SPARX5=y

0 commit comments

Comments
 (0)