Skip to content

Commit d8ece8b

Browse files
committed
Merge tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.5 Part 2 T-Head: Add a basic dtsi, Kconfig bits & trivial binding additions for the T-Head 1520 SoC (codename "light"). This SoC can be found on the Lichee Pi 4a, for which a minimal dts is added. Misc: Re-sort the dts Makefile to be in alphanumerical order by directory. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option dt-bindings: riscv: Add T-HEAD TH1520 board compatibles dt-bindings: timer: Add T-HEAD TH1520 clint dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Link: https://lore.kernel.org/r/20230620-fidelity-variety-60b47c889e31@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents d704f1f + 2bd9e07 commit d8ece8b

11 files changed

Lines changed: 543 additions & 2 deletions

File tree

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,7 @@ properties:
6565
- items:
6666
- enum:
6767
- allwinner,sun20i-d1-plic
68+
- thead,th1520-plic
6869
- const: thead,c900-plic
6970
- items:
7071
- const: sifive,plic-1.0.0
Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/riscv/thead.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: T-HEAD SoC-based boards
8+
9+
maintainers:
10+
- Jisheng Zhang <jszhang@kernel.org>
11+
12+
description:
13+
T-HEAD SoC-based boards
14+
15+
properties:
16+
$nodename:
17+
const: '/'
18+
compatible:
19+
oneOf:
20+
- description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
21+
items:
22+
- enum:
23+
- sipeed,lichee-pi-4a
24+
- const: sipeed,lichee-module-4a
25+
- const: thead,th1520
26+
27+
additionalProperties: true
28+
29+
...

Documentation/devicetree/bindings/timer/sifive,clint.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ properties:
3737
- items:
3838
- enum:
3939
- allwinner,sun20i-d1-clint
40+
- thead,th1520-clint
4041
- const: thead,c900-clint
4142
- items:
4243
- const: sifive,clint0

MAINTAINERS

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18163,6 +18163,14 @@ F: drivers/perf/riscv_pmu.c
1816318163
F: drivers/perf/riscv_pmu_legacy.c
1816418164
F: drivers/perf/riscv_pmu_sbi.c
1816518165

18166+
RISC-V THEAD SoC SUPPORT
18167+
M: Jisheng Zhang <jszhang@kernel.org>
18168+
M: Guo Ren <guoren@kernel.org>
18169+
M: Fu Wei <wefu@redhat.com>
18170+
L: linux-riscv@lists.infradead.org
18171+
S: Maintained
18172+
F: arch/riscv/boot/dts/thead/
18173+
1816618174
RNBD BLOCK DRIVERS
1816718175
M: Md. Haris Iqbal <haris.iqbal@ionos.com>
1816818176
M: Jack Wang <jinpu.wang@ionos.com>

arch/riscv/Kconfig.socs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,12 @@ config ARCH_SUNXI
4141
This enables support for Allwinner sun20i platform hardware,
4242
including boards based on the D1 and D1s SoCs.
4343

44+
config ARCH_THEAD
45+
bool "T-HEAD RISC-V SoCs"
46+
select ERRATA_THEAD
47+
help
48+
This enables support for the RISC-V based T-HEAD SoCs.
49+
4450
config ARCH_VIRT
4551
def_bool SOC_VIRT
4652

arch/riscv/boot/dts/Makefile

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
# SPDX-License-Identifier: GPL-2.0
22
subdir-y += allwinner
3-
subdir-y += sifive
4-
subdir-y += starfive
53
subdir-y += canaan
64
subdir-y += microchip
75
subdir-y += renesas
6+
subdir-y += sifive
7+
subdir-y += starfive
8+
subdir-y += thead
89

910
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

arch/riscv/boot/dts/thead/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4+
*/
5+
6+
/dts-v1/;
7+
8+
#include "th1520.dtsi"
9+
10+
/ {
11+
model = "Sipeed Lichee Module 4A";
12+
compatible = "sipeed,lichee-module-4a", "thead,th1520";
13+
14+
memory@0 {
15+
device_type = "memory";
16+
reg = <0x0 0x00000000 0x2 0x00000000>;
17+
};
18+
};
19+
20+
&osc {
21+
clock-frequency = <24000000>;
22+
};
23+
24+
&osc_32k {
25+
clock-frequency = <32768>;
26+
};
27+
28+
&apb_clk {
29+
clock-frequency = <62500000>;
30+
};
31+
32+
&uart_sclk {
33+
clock-frequency = <100000000>;
34+
};
35+
36+
&dmac0 {
37+
status = "okay";
38+
};
Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4+
*/
5+
6+
#include "th1520-lichee-module-4a.dtsi"
7+
8+
/ {
9+
model = "Sipeed Lichee Pi 4A";
10+
compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
11+
12+
aliases {
13+
gpio0 = &gpio0;
14+
gpio1 = &gpio1;
15+
gpio2 = &gpio2;
16+
gpio3 = &gpio3;
17+
serial0 = &uart0;
18+
serial1 = &uart1;
19+
serial2 = &uart2;
20+
serial3 = &uart3;
21+
serial4 = &uart4;
22+
serial5 = &uart5;
23+
};
24+
25+
chosen {
26+
stdout-path = "serial0:115200n8";
27+
};
28+
};
29+
30+
&uart0 {
31+
status = "okay";
32+
};

0 commit comments

Comments
 (0)