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perf vendor events amd: Add Zen 5 uncore events
Add uncore events taken from Section 1.5 "L3 Cache Performance Monitor Counters" and Section 2 "UMC Performance Monitors" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture L3 cache and UMC command activity. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/e11e8d9d1af34a0fb565fc9d1c4a05f569c39ddc.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎tools/perf/pmu-events/arch/x86/amdzen5/l3-cache.json‎

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[
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{
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"EventName": "l3_lookup_state.l3_miss",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache misses.",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.l3_hit",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache hits.",
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"UMask": "0xfe",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache requests for all coherent accesses.",
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"UMask": "0xff",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.near_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.far_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.all",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency from all data sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.near_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.far_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.all",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from all data sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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}
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]

‎tools/perf/pmu-events/arch/x86/amdzen5/memory-controller.json‎

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[
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{
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"EventName": "umc_mem_clk",
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"PublicDescription": "Number of memory clock (MEMCLK) cycles.",
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"EventCode": "0x00",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.all",
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"PublicDescription": "Number of ACTIVATE commands sent.",
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"EventCode": "0x05",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.rd",
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"PublicDescription": "Number of ACTIVATE commands sent for reads.",
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"EventCode": "0x05",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.wr",
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"PublicDescription": "Number of ACTIVATE commands sent for writes.",
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"EventCode": "0x05",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.all",
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"PublicDescription": "Number of PRECHARGE commands sent.",
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"EventCode": "0x06",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.rd",
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"PublicDescription": "Number of PRECHARGE commands sent for reads.",
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"EventCode": "0x06",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.wr",
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"PublicDescription": "Number of PRECHARGE commands sent for writes.",
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"EventCode": "0x06",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.all",
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"PublicDescription": "Number of CAS commands sent.",
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"EventCode": "0x0a",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.rd",
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"PublicDescription": "Number of CAS commands sent for reads.",
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"EventCode": "0x0a",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.wr",
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"PublicDescription": "Number of CAS commands sent for writes.",
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"EventCode": "0x0a",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.all",
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"PublicDescription": "Number of clock cycles used by the data bus.",
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"EventCode": "0x14",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.rd",
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"PublicDescription": "Number of clock cycles used by the data bus for reads.",
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"EventCode": "0x14",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.wr",
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"PublicDescription": "Number of clock cycles used by the data bus for writes.",
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"EventCode": "0x14",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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}
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]

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