Skip to content

Commit e6bbf39

Browse files
Mani-Sadhasivamandersson
authored andcommitted
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 parent 3c3abb9 commit e6bbf39

2 files changed

Lines changed: 56 additions & 14 deletions

File tree

arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -733,22 +733,14 @@
733733
pinctrl-0 = <&pcie4_default>;
734734

735735
status = "okay";
736+
};
736737

737-
pcie@0 {
738-
device_type = "pci";
739-
reg = <0x0 0x0 0x0 0x0 0x0>;
740-
#address-cells = <3>;
741-
#size-cells = <2>;
742-
ranges;
743-
744-
bus-range = <0x01 0xff>;
745-
746-
wifi@0 {
747-
compatible = "pci17cb,1103";
748-
reg = <0x10000 0x0 0x0 0x0 0x0>;
738+
&pcie4_port0 {
739+
wifi@0 {
740+
compatible = "pci17cb,1103";
741+
reg = <0x10000 0x0 0x0 0x0 0x0>;
749742

750-
qcom,ath11k-calibration-variant = "LE_X13S";
751-
};
743+
qcom,ath11k-calibration-variant = "LE_X13S";
752744
};
753745
};
754746

arch/arm64/boot/dts/qcom/sc8280xp.dtsi

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1803,6 +1803,16 @@
18031803
phy-names = "pciephy";
18041804

18051805
status = "disabled";
1806+
1807+
pcie4_port0: pcie@0 {
1808+
device_type = "pci";
1809+
reg = <0x0 0x0 0x0 0x0 0x0>;
1810+
bus-range = <0x01 0xff>;
1811+
1812+
#address-cells = <3>;
1813+
#size-cells = <2>;
1814+
ranges;
1815+
};
18061816
};
18071817

18081818
pcie4_phy: phy@1c06000 {
@@ -1904,6 +1914,16 @@
19041914
phy-names = "pciephy";
19051915

19061916
status = "disabled";
1917+
1918+
pcie3b_port0: pcie@0 {
1919+
device_type = "pci";
1920+
reg = <0x0 0x0 0x0 0x0 0x0>;
1921+
bus-range = <0x01 0xff>;
1922+
1923+
#address-cells = <3>;
1924+
#size-cells = <2>;
1925+
ranges;
1926+
};
19071927
};
19081928

19091929
pcie3b_phy: phy@1c0e000 {
@@ -2005,6 +2025,16 @@
20052025
phy-names = "pciephy";
20062026

20072027
status = "disabled";
2028+
2029+
pcie3a_port0: pcie@0 {
2030+
device_type = "pci";
2031+
reg = <0x0 0x0 0x0 0x0 0x0>;
2032+
bus-range = <0x01 0xff>;
2033+
2034+
#address-cells = <3>;
2035+
#size-cells = <2>;
2036+
ranges;
2037+
};
20082038
};
20092039

20102040
pcie3a_phy: phy@1c14000 {
@@ -2109,6 +2139,16 @@
21092139
phy-names = "pciephy";
21102140

21112141
status = "disabled";
2142+
2143+
pcie2b_port0: pcie@0 {
2144+
device_type = "pci";
2145+
reg = <0x0 0x0 0x0 0x0 0x0>;
2146+
bus-range = <0x01 0xff>;
2147+
2148+
#address-cells = <3>;
2149+
#size-cells = <2>;
2150+
ranges;
2151+
};
21122152
};
21132153

21142154
pcie2b_phy: phy@1c1e000 {
@@ -2210,6 +2250,16 @@
22102250
phy-names = "pciephy";
22112251

22122252
status = "disabled";
2253+
2254+
pcie2a_port0: pcie@0 {
2255+
device_type = "pci";
2256+
reg = <0x0 0x0 0x0 0x0 0x0>;
2257+
bus-range = <0x01 0xff>;
2258+
2259+
#address-cells = <3>;
2260+
#size-cells = <2>;
2261+
ranges;
2262+
};
22132263
};
22142264

22152265
pcie2a_phy: phy@1c24000 {

0 commit comments

Comments
 (0)