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1174 | 1174 | #size-cells = <1>; |
1175 | 1175 | ranges; |
1176 | 1176 |
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| 1177 | + mipi_dsi: dsi@32e60000 { |
| 1178 | + compatible = "fsl,imx8mp-mipi-dsim"; |
| 1179 | + reg = <0x32e60000 0x400>; |
| 1180 | + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, |
| 1181 | + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; |
| 1182 | + clock-names = "bus_clk", "sclk_mipi"; |
| 1183 | + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, |
| 1184 | + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; |
| 1185 | + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, |
| 1186 | + <&clk IMX8MP_CLK_24M>; |
| 1187 | + assigned-clock-rates = <200000000>, <24000000>; |
| 1188 | + samsung,pll-clock-frequency = <24000000>; |
| 1189 | + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| 1190 | + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; |
| 1191 | + status = "disabled"; |
| 1192 | + |
| 1193 | + ports { |
| 1194 | + #address-cells = <1>; |
| 1195 | + #size-cells = <0>; |
| 1196 | + |
| 1197 | + port@0 { |
| 1198 | + reg = <0>; |
| 1199 | + |
| 1200 | + dsim_from_lcdif1: endpoint { |
| 1201 | + remote-endpoint = <&lcdif1_to_dsim>; |
| 1202 | + }; |
| 1203 | + }; |
| 1204 | + }; |
| 1205 | + }; |
| 1206 | + |
| 1207 | + lcdif1: display-controller@32e80000 { |
| 1208 | + compatible = "fsl,imx8mp-lcdif"; |
| 1209 | + reg = <0x32e80000 0x10000>; |
| 1210 | + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, |
| 1211 | + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, |
| 1212 | + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; |
| 1213 | + clock-names = "pix", "axi", "disp_axi"; |
| 1214 | + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, |
| 1215 | + <&clk IMX8MP_CLK_MEDIA_AXI>, |
| 1216 | + <&clk IMX8MP_CLK_MEDIA_APB>; |
| 1217 | + assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, |
| 1218 | + <&clk IMX8MP_SYS_PLL2_1000M>, |
| 1219 | + <&clk IMX8MP_SYS_PLL1_800M>; |
| 1220 | + assigned-clock-rates = <594000000>, <500000000>, <200000000>; |
| 1221 | + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 1222 | + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; |
| 1223 | + status = "disabled"; |
| 1224 | + |
| 1225 | + port { |
| 1226 | + lcdif1_to_dsim: endpoint { |
| 1227 | + remote-endpoint = <&dsim_from_lcdif1>; |
| 1228 | + }; |
| 1229 | + }; |
| 1230 | + }; |
| 1231 | + |
1177 | 1232 | lcdif2: display-controller@32e90000 { |
1178 | 1233 | compatible = "fsl,imx8mp-lcdif"; |
1179 | 1234 | reg = <0x32e90000 0x238>; |
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