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Marek VasutShawn Guo
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arm64: dts: imx8mp: Add display pipeline components
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus. This makes the DSI display pipeline available on this SoC. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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arch/arm64/boot/dts/freescale/imx8mp.dtsi

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@@ -1174,6 +1174,61 @@
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#size-cells = <1>;
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ranges;
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mipi_dsi: dsi@32e60000 {
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compatible = "fsl,imx8mp-mipi-dsim";
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reg = <0x32e60000 0x400>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
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clock-names = "bus_clk", "sclk_mipi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_CLK_24M>;
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assigned-clock-rates = <200000000>, <24000000>;
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samsung,pll-clock-frequency = <24000000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsim_from_lcdif1: endpoint {
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remote-endpoint = <&lcdif1_to_dsim>;
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};
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};
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};
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};
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lcdif1: display-controller@32e80000 {
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compatible = "fsl,imx8mp-lcdif";
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reg = <0x32e80000 0x10000>;
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clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
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clock-names = "pix", "axi", "disp_axi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI>,
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<&clk IMX8MP_CLK_MEDIA_APB>;
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assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
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<&clk IMX8MP_SYS_PLL2_1000M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <594000000>, <500000000>, <200000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
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status = "disabled";
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port {
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lcdif1_to_dsim: endpoint {
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remote-endpoint = <&dsim_from_lcdif1>;
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};
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};
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};
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lcdif2: display-controller@32e90000 {
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compatible = "fsl,imx8mp-lcdif";
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reg = <0x32e90000 0x238>;

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