Skip to content

Commit edd13c0

Browse files
konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
committed
interconnect: qcom: sm8350: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-19-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
1 parent 8e509d6 commit edd13c0

1 file changed

Lines changed: 276 additions & 32 deletions

File tree

‎drivers/interconnect/qcom/sm8350.c‎

Lines changed: 276 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1354,38 +1354,282 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
13541354
.links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
13551355
};
13561356

1357-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1358-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1359-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
1360-
DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
1361-
DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
1362-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
1363-
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
1364-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1365-
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1366-
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
1367-
DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
1368-
DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
1369-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1370-
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
1371-
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
1372-
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
1373-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1374-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
1375-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
1376-
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
1377-
DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
1378-
DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
1379-
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
1380-
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
1381-
DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
1382-
DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
1383-
DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
1384-
DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
1385-
DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
1386-
DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
1387-
DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
1388-
DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
1357+
static struct qcom_icc_bcm bcm_acv = {
1358+
.name = "ACV",
1359+
.keepalive = false,
1360+
.num_nodes = 1,
1361+
.nodes = { &ebi },
1362+
};
1363+
1364+
static struct qcom_icc_bcm bcm_ce0 = {
1365+
.name = "CE0",
1366+
.keepalive = false,
1367+
.num_nodes = 1,
1368+
.nodes = { &qxm_crypto },
1369+
};
1370+
1371+
static struct qcom_icc_bcm bcm_cn0 = {
1372+
.name = "CN0",
1373+
.keepalive = true,
1374+
.num_nodes = 2,
1375+
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1376+
};
1377+
1378+
static struct qcom_icc_bcm bcm_cn1 = {
1379+
.name = "CN1",
1380+
.keepalive = false,
1381+
.num_nodes = 47,
1382+
.nodes = { &xm_qdss_dap,
1383+
&qhs_ahb2phy0,
1384+
&qhs_ahb2phy1,
1385+
&qhs_aoss,
1386+
&qhs_apss,
1387+
&qhs_camera_cfg,
1388+
&qhs_clk_ctl,
1389+
&qhs_compute_cfg,
1390+
&qhs_cpr_cx,
1391+
&qhs_cpr_mmcx,
1392+
&qhs_cpr_mx,
1393+
&qhs_crypto0_cfg,
1394+
&qhs_cx_rdpm,
1395+
&qhs_dcc_cfg,
1396+
&qhs_display_cfg,
1397+
&qhs_gpuss_cfg,
1398+
&qhs_hwkm,
1399+
&qhs_imem_cfg,
1400+
&qhs_ipa,
1401+
&qhs_ipc_router,
1402+
&qhs_mss_cfg,
1403+
&qhs_mx_rdpm,
1404+
&qhs_pcie0_cfg,
1405+
&qhs_pcie1_cfg,
1406+
&qhs_pimem_cfg,
1407+
&qhs_pka_wrapper_cfg,
1408+
&qhs_pmu_wrapper_cfg,
1409+
&qhs_qdss_cfg,
1410+
&qhs_qup0,
1411+
&qhs_qup1,
1412+
&qhs_qup2,
1413+
&qhs_security,
1414+
&qhs_spss_cfg,
1415+
&qhs_tcsr,
1416+
&qhs_tlmm,
1417+
&qhs_ufs_card_cfg,
1418+
&qhs_ufs_mem_cfg,
1419+
&qhs_usb3_0,
1420+
&qhs_usb3_1,
1421+
&qhs_venus_cfg,
1422+
&qhs_vsense_ctrl_cfg,
1423+
&qns_a1_noc_cfg,
1424+
&qns_a2_noc_cfg,
1425+
&qns_ddrss_cfg,
1426+
&qns_mnoc_cfg,
1427+
&qns_snoc_cfg,
1428+
&srvc_cnoc
1429+
},
1430+
};
1431+
1432+
static struct qcom_icc_bcm bcm_cn2 = {
1433+
.name = "CN2",
1434+
.keepalive = false,
1435+
.num_nodes = 5,
1436+
.nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 },
1437+
};
1438+
1439+
static struct qcom_icc_bcm bcm_co0 = {
1440+
.name = "CO0",
1441+
.keepalive = false,
1442+
.num_nodes = 1,
1443+
.nodes = { &qns_nsp_gemnoc },
1444+
};
1445+
1446+
static struct qcom_icc_bcm bcm_co3 = {
1447+
.name = "CO3",
1448+
.keepalive = false,
1449+
.num_nodes = 1,
1450+
.nodes = { &qxm_nsp },
1451+
};
1452+
1453+
static struct qcom_icc_bcm bcm_mc0 = {
1454+
.name = "MC0",
1455+
.keepalive = true,
1456+
.num_nodes = 1,
1457+
.nodes = { &ebi },
1458+
};
1459+
1460+
static struct qcom_icc_bcm bcm_mm0 = {
1461+
.name = "MM0",
1462+
.keepalive = true,
1463+
.num_nodes = 1,
1464+
.nodes = { &qns_mem_noc_hf },
1465+
};
1466+
1467+
static struct qcom_icc_bcm bcm_mm1 = {
1468+
.name = "MM1",
1469+
.keepalive = false,
1470+
.num_nodes = 3,
1471+
.nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 },
1472+
};
1473+
1474+
static struct qcom_icc_bcm bcm_mm4 = {
1475+
.name = "MM4",
1476+
.keepalive = false,
1477+
.num_nodes = 1,
1478+
.nodes = { &qns_mem_noc_sf },
1479+
};
1480+
1481+
static struct qcom_icc_bcm bcm_mm5 = {
1482+
.name = "MM5",
1483+
.keepalive = false,
1484+
.num_nodes = 6,
1485+
.nodes = { &qnm_camnoc_icp,
1486+
&qnm_camnoc_sf,
1487+
&qnm_video0,
1488+
&qnm_video1,
1489+
&qnm_video_cvp,
1490+
&qxm_rot
1491+
},
1492+
};
1493+
1494+
static struct qcom_icc_bcm bcm_sh0 = {
1495+
.name = "SH0",
1496+
.keepalive = true,
1497+
.num_nodes = 1,
1498+
.nodes = { &qns_llcc },
1499+
};
1500+
1501+
static struct qcom_icc_bcm bcm_sh2 = {
1502+
.name = "SH2",
1503+
.keepalive = false,
1504+
.num_nodes = 2,
1505+
.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1506+
};
1507+
1508+
static struct qcom_icc_bcm bcm_sh3 = {
1509+
.name = "SH3",
1510+
.keepalive = false,
1511+
.num_nodes = 1,
1512+
.nodes = { &qnm_cmpnoc },
1513+
};
1514+
1515+
static struct qcom_icc_bcm bcm_sh4 = {
1516+
.name = "SH4",
1517+
.keepalive = false,
1518+
.num_nodes = 1,
1519+
.nodes = { &chm_apps },
1520+
};
1521+
1522+
static struct qcom_icc_bcm bcm_sn0 = {
1523+
.name = "SN0",
1524+
.keepalive = true,
1525+
.num_nodes = 1,
1526+
.nodes = { &qns_gemnoc_sf },
1527+
};
1528+
1529+
static struct qcom_icc_bcm bcm_sn2 = {
1530+
.name = "SN2",
1531+
.keepalive = false,
1532+
.num_nodes = 1,
1533+
.nodes = { &qns_gemnoc_gc },
1534+
};
1535+
1536+
static struct qcom_icc_bcm bcm_sn3 = {
1537+
.name = "SN3",
1538+
.keepalive = false,
1539+
.num_nodes = 1,
1540+
.nodes = { &qxs_pimem },
1541+
};
1542+
1543+
static struct qcom_icc_bcm bcm_sn4 = {
1544+
.name = "SN4",
1545+
.keepalive = false,
1546+
.num_nodes = 1,
1547+
.nodes = { &xs_qdss_stm },
1548+
};
1549+
1550+
static struct qcom_icc_bcm bcm_sn5 = {
1551+
.name = "SN5",
1552+
.keepalive = false,
1553+
.num_nodes = 1,
1554+
.nodes = { &xm_pcie3_0 },
1555+
};
1556+
1557+
static struct qcom_icc_bcm bcm_sn6 = {
1558+
.name = "SN6",
1559+
.keepalive = false,
1560+
.num_nodes = 1,
1561+
.nodes = { &xm_pcie3_1 },
1562+
};
1563+
1564+
static struct qcom_icc_bcm bcm_sn7 = {
1565+
.name = "SN7",
1566+
.keepalive = false,
1567+
.num_nodes = 1,
1568+
.nodes = { &qnm_aggre1_noc },
1569+
};
1570+
1571+
static struct qcom_icc_bcm bcm_sn8 = {
1572+
.name = "SN8",
1573+
.keepalive = false,
1574+
.num_nodes = 1,
1575+
.nodes = { &qnm_aggre2_noc },
1576+
};
1577+
1578+
static struct qcom_icc_bcm bcm_sn14 = {
1579+
.name = "SN14",
1580+
.keepalive = false,
1581+
.num_nodes = 1,
1582+
.nodes = { &qns_pcie_mem_noc },
1583+
};
1584+
1585+
static struct qcom_icc_bcm bcm_acv_disp = {
1586+
.name = "ACV",
1587+
.keepalive = false,
1588+
.num_nodes = 1,
1589+
.nodes = { &ebi_disp },
1590+
};
1591+
1592+
static struct qcom_icc_bcm bcm_mc0_disp = {
1593+
.name = "MC0",
1594+
.keepalive = false,
1595+
.num_nodes = 1,
1596+
.nodes = { &ebi_disp },
1597+
};
1598+
1599+
static struct qcom_icc_bcm bcm_mm0_disp = {
1600+
.name = "MM0",
1601+
.keepalive = false,
1602+
.num_nodes = 1,
1603+
.nodes = { &qns_mem_noc_hf_disp },
1604+
};
1605+
1606+
static struct qcom_icc_bcm bcm_mm1_disp = {
1607+
.name = "MM1",
1608+
.keepalive = false,
1609+
.num_nodes = 2,
1610+
.nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp },
1611+
};
1612+
1613+
static struct qcom_icc_bcm bcm_mm4_disp = {
1614+
.name = "MM4",
1615+
.keepalive = false,
1616+
.num_nodes = 1,
1617+
.nodes = { &qns_mem_noc_sf_disp },
1618+
};
1619+
1620+
static struct qcom_icc_bcm bcm_mm5_disp = {
1621+
.name = "MM5",
1622+
.keepalive = false,
1623+
.num_nodes = 1,
1624+
.nodes = { &qxm_rot_disp },
1625+
};
1626+
1627+
static struct qcom_icc_bcm bcm_sh0_disp = {
1628+
.name = "SH0",
1629+
.keepalive = false,
1630+
.num_nodes = 1,
1631+
.nodes = { &qns_llcc_disp },
1632+
};
13891633

13901634
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
13911635
};

0 commit comments

Comments
 (0)