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ashoksomamichalsimek
ashoksoma
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michalsimek
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arm64: zynqmp: Fix usb node drive strength and slew rate
As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
1 parent c720a1f commit f8673fd

10 files changed

Lines changed: 54 additions & 18 deletions

‎arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for KV260 revA Carrier Card
44
*
5-
* (C) Copyright 2020 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2020 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* SD level shifter:
89
* "A" - A01 board un-modified (NXP)
@@ -265,19 +266,22 @@
265266
pinctrl_usb0_default: usb0-default {
266267
conf {
267268
groups = "usb0_0_grp";
268-
slew-rate = <SLEW_RATE_SLOW>;
269269
power-source = <IO_STANDARD_LVCMOS18>;
270270
};
271271

272272
conf-rx {
273273
pins = "MIO52", "MIO53", "MIO55";
274274
bias-high-impedance;
275+
drive-strength = <12>;
276+
slew-rate = <SLEW_RATE_FAST>;
275277
};
276278

277279
conf-tx {
278280
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
279281
"MIO60", "MIO61", "MIO62", "MIO63";
280282
bias-disable;
283+
drive-strength = <4>;
284+
slew-rate = <SLEW_RATE_SLOW>;
281285
};
282286

283287
mux {

‎arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for KV260 revA Carrier Card
44
*
5-
* (C) Copyright 2020 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2020 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -248,19 +249,22 @@
248249
pinctrl_usb0_default: usb0-default {
249250
conf {
250251
groups = "usb0_0_grp";
251-
slew-rate = <SLEW_RATE_SLOW>;
252252
power-source = <IO_STANDARD_LVCMOS18>;
253253
};
254254

255255
conf-rx {
256256
pins = "MIO52", "MIO53", "MIO55";
257257
bias-high-impedance;
258+
drive-strength = <12>;
259+
slew-rate = <SLEW_RATE_FAST>;
258260
};
259261

260262
conf-tx {
261263
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
262264
"MIO60", "MIO61", "MIO62", "MIO63";
263265
bias-disable;
266+
drive-strength = <4>;
267+
slew-rate = <SLEW_RATE_SLOW>;
264268
};
265269

266270
mux {

‎arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
44
*
5-
* (C) Copyright 2015 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2015 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -187,19 +188,22 @@
187188

188189
conf {
189190
groups = "usb0_0_grp";
190-
slew-rate = <SLEW_RATE_SLOW>;
191191
power-source = <IO_STANDARD_LVCMOS18>;
192192
};
193193

194194
conf-rx {
195195
pins = "MIO52", "MIO53", "MIO55";
196196
bias-high-impedance;
197+
drive-strength = <12>;
198+
slew-rate = <SLEW_RATE_FAST>;
197199
};
198200

199201
conf-tx {
200202
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
201203
"MIO60", "MIO61", "MIO62", "MIO63";
202204
bias-disable;
205+
drive-strength = <4>;
206+
slew-rate = <SLEW_RATE_SLOW>;
203207
};
204208
};
205209

‎arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
44
*
5-
* (C) Copyright 2015 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2015 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -281,19 +282,22 @@
281282

282283
conf {
283284
groups = "usb1_0_grp";
284-
slew-rate = <SLEW_RATE_SLOW>;
285285
power-source = <IO_STANDARD_LVCMOS18>;
286286
};
287287

288288
conf-rx {
289289
pins = "MIO64", "MIO65", "MIO67";
290290
bias-high-impedance;
291+
drive-strength = <12>;
292+
slew-rate = <SLEW_RATE_FAST>;
291293
};
292294

293295
conf-tx {
294296
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
295297
"MIO72", "MIO73", "MIO74", "MIO75";
296298
bias-disable;
299+
drive-strength = <4>;
300+
slew-rate = <SLEW_RATE_SLOW>;
297301
};
298302
};
299303

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU100 revC
44
*
5-
* (C) Copyright 2016 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2016 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
* Nathalie Chan King Choy
@@ -432,19 +433,22 @@
432433

433434
conf {
434435
groups = "usb0_0_grp";
435-
slew-rate = <SLEW_RATE_SLOW>;
436436
power-source = <IO_STANDARD_LVCMOS18>;
437437
};
438438

439439
conf-rx {
440440
pins = "MIO52", "MIO53", "MIO55";
441441
bias-high-impedance;
442+
drive-strength = <12>;
443+
slew-rate = <SLEW_RATE_FAST>;
442444
};
443445

444446
conf-tx {
445447
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
446448
"MIO60", "MIO61", "MIO62", "MIO63";
447449
bias-disable;
450+
drive-strength = <4>;
451+
slew-rate = <SLEW_RATE_SLOW>;
448452
};
449453
};
450454

@@ -456,19 +460,22 @@
456460

457461
conf {
458462
groups = "usb1_0_grp";
459-
slew-rate = <SLEW_RATE_SLOW>;
460463
power-source = <IO_STANDARD_LVCMOS18>;
461464
};
462465

463466
conf-rx {
464467
pins = "MIO64", "MIO65", "MIO67";
465468
bias-high-impedance;
469+
drive-strength = <12>;
470+
slew-rate = <SLEW_RATE_FAST>;
466471
};
467472

468473
conf-tx {
469474
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
470475
"MIO72", "MIO73", "MIO74", "MIO75";
471476
bias-disable;
477+
drive-strength = <4>;
478+
slew-rate = <SLEW_RATE_SLOW>;
472479
};
473480
};
474481
};

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -783,19 +783,22 @@
783783

784784
conf {
785785
groups = "usb0_0_grp";
786-
slew-rate = <SLEW_RATE_SLOW>;
787786
power-source = <IO_STANDARD_LVCMOS18>;
788787
};
789788

790789
conf-rx {
791790
pins = "MIO52", "MIO53", "MIO55";
792791
bias-high-impedance;
792+
drive-strength = <12>;
793+
slew-rate = <SLEW_RATE_FAST>;
793794
};
794795

795796
conf-tx {
796797
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
797798
"MIO60", "MIO61", "MIO62", "MIO63";
798799
bias-disable;
800+
drive-strength = <4>;
801+
slew-rate = <SLEW_RATE_SLOW>;
799802
};
800803
};
801804

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -410,20 +410,22 @@
410410

411411
conf {
412412
groups = "usb0_0_grp";
413-
slew-rate = <SLEW_RATE_SLOW>;
414413
power-source = <IO_STANDARD_LVCMOS18>;
415-
drive-strength = <12>;
416414
};
417415

418416
conf-rx {
419417
pins = "MIO52", "MIO53", "MIO55";
420418
bias-high-impedance;
419+
drive-strength = <12>;
420+
slew-rate = <SLEW_RATE_FAST>;
421421
};
422422

423423
conf-tx {
424424
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
425425
"MIO60", "MIO61", "MIO62", "MIO63";
426426
bias-disable;
427+
drive-strength = <4>;
428+
slew-rate = <SLEW_RATE_SLOW>;
427429
};
428430
};
429431
};

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -422,20 +422,22 @@
422422

423423
conf {
424424
groups = "usb0_0_grp";
425-
slew-rate = <SLEW_RATE_SLOW>;
426425
power-source = <IO_STANDARD_LVCMOS18>;
427-
drive-strength = <12>;
428426
};
429427

430428
conf-rx {
431429
pins = "MIO52", "MIO53", "MIO55";
432430
bias-high-impedance;
431+
drive-strength = <12>;
432+
slew-rate = <SLEW_RATE_FAST>;
433433
};
434434

435435
conf-tx {
436436
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
437437
"MIO60", "MIO61", "MIO62", "MIO63";
438438
bias-disable;
439+
drive-strength = <4>;
440+
slew-rate = <SLEW_RATE_SLOW>;
439441
};
440442
};
441443
};

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -794,19 +794,22 @@
794794

795795
conf {
796796
groups = "usb0_0_grp";
797-
slew-rate = <SLEW_RATE_SLOW>;
798797
power-source = <IO_STANDARD_LVCMOS18>;
799798
};
800799

801800
conf-rx {
802801
pins = "MIO52", "MIO53", "MIO55";
803802
bias-high-impedance;
803+
drive-strength = <12>;
804+
slew-rate = <SLEW_RATE_FAST>;
804805
};
805806

806807
conf-tx {
807808
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
808809
"MIO60", "MIO61", "MIO62", "MIO63";
809810
bias-disable;
811+
drive-strength = <4>;
812+
slew-rate = <SLEW_RATE_SLOW>;
810813
};
811814
};
812815

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -660,19 +660,22 @@
660660

661661
conf {
662662
groups = "usb0_0_grp";
663-
slew-rate = <SLEW_RATE_SLOW>;
664663
power-source = <IO_STANDARD_LVCMOS18>;
665664
};
666665

667666
conf-rx {
668667
pins = "MIO52", "MIO53", "MIO55";
669668
bias-high-impedance;
669+
drive-strength = <12>;
670+
slew-rate = <SLEW_RATE_FAST>;
670671
};
671672

672673
conf-tx {
673674
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
674675
"MIO60", "MIO61", "MIO62", "MIO63";
675676
bias-disable;
677+
drive-strength = <4>;
678+
slew-rate = <SLEW_RATE_SLOW>;
676679
};
677680
};
678681

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