|
29 | 29 | stdout-path = "serial2:115200n8"; |
30 | 30 | }; |
31 | 31 |
|
| 32 | + backlight: backlight { |
| 33 | + compatible = "pwm-backlight"; |
| 34 | + pwms = <&pwm0 0 50000 0>; |
| 35 | + }; |
| 36 | + |
32 | 37 | gpio-keys { |
33 | 38 | compatible = "gpio-keys"; |
34 | 39 | pinctrl-names = "default"; |
|
102 | 107 | /* WL_REG_ON on module */ |
103 | 108 | reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; |
104 | 109 | }; |
| 110 | + |
| 111 | + /* MIPI DSI panel 1.8v supply */ |
| 112 | + vcc1v8_lcd: vcc1v8-lcd { |
| 113 | + compatible = "regulator-fixed"; |
| 114 | + enable-active-high; |
| 115 | + regulator-name = "vcc1v8_lcd"; |
| 116 | + regulator-min-microvolt = <1800000>; |
| 117 | + regulator-max-microvolt = <1800000>; |
| 118 | + vin-supply = <&vcc3v3_sys>; |
| 119 | + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; |
| 120 | + pinctrl-names = "default"; |
| 121 | + }; |
| 122 | + |
| 123 | + /* MIPI DSI panel 2.8v supply */ |
| 124 | + vcc2v8_lcd: vcc2v8-lcd { |
| 125 | + compatible = "regulator-fixed"; |
| 126 | + enable-active-high; |
| 127 | + regulator-name = "vcc2v8_lcd"; |
| 128 | + regulator-min-microvolt = <2800000>; |
| 129 | + regulator-max-microvolt = <2800000>; |
| 130 | + vin-supply = <&vcc3v3_sys>; |
| 131 | + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; |
| 132 | + pinctrl-names = "default"; |
| 133 | + }; |
105 | 134 | }; |
106 | 135 |
|
107 | 136 | &cpu_alert0 { |
|
139 | 168 | status = "okay"; |
140 | 169 | }; |
141 | 170 |
|
| 171 | +&gpu { |
| 172 | + mali-supply = <&vdd_gpu>; |
| 173 | + status = "okay"; |
| 174 | +}; |
| 175 | + |
142 | 176 | &i2c0 { |
143 | 177 | clock-frequency = <400000>; |
144 | 178 | i2c-scl-rising-time-ns = <168>; |
|
333 | 367 | }; |
334 | 368 | }; |
335 | 369 |
|
| 370 | +&i2c3 { |
| 371 | + i2c-scl-rising-time-ns = <450>; |
| 372 | + i2c-scl-falling-time-ns = <15>; |
| 373 | + status = "okay"; |
| 374 | + |
| 375 | + touchscreen@14 { |
| 376 | + compatible = "goodix,gt1158"; |
| 377 | + reg = <0x14>; |
| 378 | + interrupt-parent = <&gpio3>; |
| 379 | + interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>; |
| 380 | + irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; |
| 381 | + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; |
| 382 | + AVDD28-supply = <&vcc3v0_touch>; |
| 383 | + VDDIO-supply = <&vcc3v0_touch>; |
| 384 | + touchscreen-size-x = <720>; |
| 385 | + touchscreen-size-y = <1440>; |
| 386 | + }; |
| 387 | +}; |
| 388 | + |
336 | 389 | &cluster0_opp { |
337 | 390 | opp04 { |
338 | 391 | status = "disabled"; |
|
362 | 415 | status = "okay"; |
363 | 416 | }; |
364 | 417 |
|
| 418 | +&mipi_dsi { |
| 419 | + status = "okay"; |
| 420 | + clock-master; |
| 421 | + |
| 422 | + ports { |
| 423 | + mipi_out: port@1 { |
| 424 | + #address-cells = <0>; |
| 425 | + #size-cells = <0>; |
| 426 | + reg = <1>; |
| 427 | + |
| 428 | + mipi_out_panel: endpoint { |
| 429 | + remote-endpoint = <&mipi_in_panel>; |
| 430 | + }; |
| 431 | + }; |
| 432 | + }; |
| 433 | + |
| 434 | + panel@0 { |
| 435 | + compatible = "hannstar,hsd060bhw4"; |
| 436 | + reg = <0>; |
| 437 | + backlight = <&backlight>; |
| 438 | + reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; |
| 439 | + vcc-supply = <&vcc2v8_lcd>; |
| 440 | + iovcc-supply = <&vcc1v8_lcd>; |
| 441 | + pinctrl-names = "default"; |
| 442 | + |
| 443 | + port { |
| 444 | + mipi_in_panel: endpoint { |
| 445 | + remote-endpoint = <&mipi_out_panel>; |
| 446 | + }; |
| 447 | + }; |
| 448 | + }; |
| 449 | +}; |
| 450 | + |
365 | 451 | &pmu_io_domains { |
366 | 452 | pmu1830-supply = <&vcc_1v8>; |
367 | 453 | status = "okay"; |
|
429 | 515 | status = "okay"; |
430 | 516 | }; |
431 | 517 |
|
| 518 | +&pwm0 { |
| 519 | + status = "okay"; |
| 520 | +}; |
| 521 | + |
432 | 522 | &sdmmc { |
433 | 523 | bus-width = <4>; |
434 | 524 | cap-sd-highspeed; |
|
479 | 569 | &uart2 { |
480 | 570 | status = "okay"; |
481 | 571 | }; |
| 572 | + |
| 573 | +&vopb { |
| 574 | + status = "okay"; |
| 575 | + assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, |
| 576 | + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; |
| 577 | + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; |
| 578 | + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; |
| 579 | +}; |
| 580 | + |
| 581 | +&vopb_mmu { |
| 582 | + status = "okay"; |
| 583 | +}; |
| 584 | + |
| 585 | +&vopl { |
| 586 | + status = "okay"; |
| 587 | + assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, |
| 588 | + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; |
| 589 | + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; |
| 590 | + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; |
| 591 | +}; |
| 592 | + |
| 593 | +&vopl_mmu { |
| 594 | + status = "okay"; |
| 595 | +}; |
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