cpufeatures: requesting support for the newly added target features

[sayantn]

Some new target features were added to Rust

• sha512, sm3 and sm4 (added in cpufeatures: x86 support of sha512, sm3, sm4 #1181)
• avxifma, avxvnni, avxvnniint8, avxvnniint16 and avxneconvert (Expand avx512_target_feature to include VEX variants rust-lang/rust#126617)
• amx-tile, amx-int8, amx-bf16, amx-fp16 and amx-complex (Add AMX target-features and x86_amx_intrinsics feature flag rust-lang/rust#126639)
• many new AArch64 target features (rustc_target: Add various aarch64 features rust-lang/rust#128192)

[tarcieri]

TIL there are SHA-512 intrinsics for x86 CPUs. Apparently only for Arrow Lake and Lunar Lake:

https://en.wikipedia.org/wiki/Intel_SHA_extensions

• VSHA512RNDS2
• VSHA512MSG1
• VSHA512MSG2

[kayabaNerve]

I'd like to follow up on this, specifically due to my interest in avxifma. I tried to do the PR myself, believing it to solely be a single line, and while I found an Intel manual specifying it's EAX bit 23 for leaf 07H, subleaf 1, I'm completely unsure what the other arguments to the macro are ("ymm"/"zmm"?).

[newpavlov]

I'm completely unsure what the other arguments to the macro are ("ymm"/"zmm"?)

It's an additional check for the register class support (see #793). IIUC avxfma and VSHA512 instructions work over XMM and YMM registers, so we don't need the ZMM check, but it's worth to consult with Intel docs regarding this matter.