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flow: add CVA6 support for Nangate45 #4428

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d840449
flow: add CVA6 support for Nangate45
HectorRguez Aug 14, 2026
2889e56
flow: remove obsolete CVA6 false path
HectorRguez Aug 14, 2026
8314c10
flow: remove duplicate CVA6 FakeRAM attributes
HectorRguez Aug 14, 2026
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3 changes: 3 additions & 0 deletions flow/designs/nangate45/cva6/BUILD
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load("//flow/designs:design.bzl", "design")

design(config = "config.mk")
4 changes: 4 additions & 0 deletions flow/designs/nangate45/cva6/canonicalize.tcl
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# Remove rvfi_probes_o interface since contributes 4k ports and connections
# (many of which are buffers tied to tie cells)

delete cva6/o:rvfi_probes_o*
106 changes: 106 additions & 0 deletions flow/designs/nangate45/cva6/config.mk
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export PLATFORM = nangate45

export DESIGN_NAME = cva6

# Some files are listed specifically vs. sorted wildcard to control the order
# (makes Verific happy)
export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)
export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \
$(SRC_HOME)/core/include/config_pkg.sv \
$(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \
$(SRC_HOME)/core/include/riscv_pkg.sv \
$(SRC_HOME)/core/include/ariane_pkg.sv \
$(SRC_HOME)/core/include/build_config_pkg.sv \
$(SRC_HOME)/core/include/std_cache_pkg.sv \
$(SRC_HOME)/core/include/wt_cache_pkg.sv \
$(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \
$(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \
$(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \
$(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \
$(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \
$(sort $(wildcard $(SRC_HOME)/core/*.sv)) \
$(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \
$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \
$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \
$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \
$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \
$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \
$(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \
$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v

export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include

export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_64x256.lef \
$(PLATFORM_DIR)/lef/fakeram45_128x64.lef \
$(PLATFORM_DIR)/lef/fakeram45_64x28.lef \
$(PLATFORM_DIR)/lef/fakeram45_64x25.lef

export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_64x256.lib \
$(PLATFORM_DIR)/lib/fakeram45_128x64.lib \
$(PLATFORM_DIR)/lib/fakeram45_64x28.lib \
$(PLATFORM_DIR)/lib/fakeram45_64x25.lib

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export CORE_UTILIZATION = 60
export CORE_MARGIN = 2
export MACRO_PLACE_HALO = 10 10
export PLACE_DENSITY = 0.75

# a smoketest for this option, there are a
# few last gasp iterations
#export SKIP_LAST_GASP ?= 1

# For use with SYNTH_HIERARCHICAL
export SYNTH_MINIMUM_KEEP_SIZE ?= 40000

export SYNTH_HDL_FRONTEND = slang

# Remove rvfi_probes_o interface
export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl

export SWAP_ARITH_OPERATORS = 1
export OPENROAD_HIERARCHICAL = 1
36 changes: 36 additions & 0 deletions flow/designs/nangate45/cva6/constraint.sdc
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# Derived from cva6_synth.tcl and Makefiles

set clk_name main_clk
set clk_port clk_i
set clk_ports_list [list $clk_port]
set clk_period 1000
set input_delay 0.46
set output_delay 0.11
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

# #set_dont_touch to keep sram as black boxes
# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[*].i_tag_sram
# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[*].i_data_sram
# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram
# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram
# #constraint the timing to and from the sram black boxes
# set_input_delay -clock main_clk -max $input_delay \
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
# set_input_delay -clock main_clk -max $input_delay \
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
# set_input_delay -clock main_clk -max $input_delay \
# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
# set_input_delay -clock main_clk -max $input_delay \
# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]

# set_output_delay $output_delay -max -clock main_clk \
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
# set_output_delay $output_delay -max -clock main_clk \
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
# set_output_delay $output_delay -max -clock main_clk \
# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
# set_output_delay $output_delay -max -clock main_clk \
# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]


set_max_fanout 10 [current_design]
75 changes: 75 additions & 0 deletions flow/designs/nangate45/cva6/macros.v
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module fakeram7_64x256 (
output [255:0] rd_out,
input [5:0] addr_in,
input we_in,
input [255:0] wd_in,
input clk,
input ce_in
);
fakeram45_64x256 mem (
.rd_out(rd_out),
.addr_in(addr_in),
.we_in(we_in),
.wd_in(wd_in),
.w_mask_in({256{1'b1}}),
.clk(clk),
.ce_in(ce_in)
);
endmodule

module fakeram7_128x64 (
output [63:0] rd_out,
input [6:0] addr_in,
input we_in,
input [63:0] wd_in,
input clk,
input ce_in
);
fakeram45_128x64 mem (
.rd_out(rd_out),
.addr_in(addr_in),
.we_in(we_in),
.wd_in(wd_in),
.w_mask_in({64{1'b1}}),
.clk(clk),
.ce_in(ce_in)
);
endmodule

module fakeram7_64x28 (
output [27:0] rd_out,
input [5:0] addr_in,
input we_in,
input [27:0] wd_in,
input clk,
input ce_in
);
fakeram45_64x28 mem (
.rd_out(rd_out),
.addr_in(addr_in),
.we_in(we_in),
.wd_in(wd_in),
.w_mask_in({28{1'b1}}),
.clk(clk),
.ce_in(ce_in)
);
endmodule

module fakeram7_64x25 (
output [24:0] rd_out,
input [5:0] addr_in,
input we_in,
input [24:0] wd_in,
input clk,
input ce_in
);
fakeram45_64x25 mem (
.rd_out(rd_out),
.addr_in(addr_in),
.we_in(we_in),
.wd_in(wd_in),
.w_mask_in({25{1'b1}}),
.clk(clk),
.ce_in(ce_in)
);
endmodule
112 changes: 112 additions & 0 deletions flow/designs/nangate45/cva6/rules-base.json
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{
"synth__canonical_netlist__hash": {
"value": "a6e7399ec64d71ce8fec5c22f41a539dd3c51090",
"compare": "==",
"level": "warning"
},
"synth__netlist__hash": {
"value": "b71fbf82e3881b7cbe01957220b1b9b8ec605e5c",
"compare": "==",
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 178000.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 286611,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 117185,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 10190,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 10190,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -50.0,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -200.0,
"compare": ">="
},
"cts__timing__hold__ws": {
"value": -50.0,
"compare": ">="
},
"cts__timing__hold__tns": {
"value": -200.0,
"compare": ">="
},
"globalroute__antenna_diodes_count": {
"value": 115,
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -50.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -200.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
"value": -50.0,
"compare": ">="
},
"globalroute__timing__hold__tns": {
"value": -200.0,
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 2496218,
"compare": "<="
},
"detailedroute__route__drc_errors": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
"value": 115,
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -50.0,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -200.0,
"compare": ">="
},
"finish__timing__hold__ws": {
"value": -50.0,
"compare": ">="
},
"finish__timing__hold__tns": {
"value": -200.0,
"compare": ">="
},
"finish__design__instance__area": {
"value": 289845,
"compare": "<="
}
}
5 changes: 5 additions & 0 deletions flow/platforms/nangate45/fakeram.cfg
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Expand Up @@ -15,6 +15,7 @@
# fakeram45_64x64 snapHeight_nm = 62200
# fakeram45_64x96 snapHeight_nm = 44700
# fakeram45_64x124 snapHeight_nm = 112600
# fakeram45_64x256 snapHeight_nm = 223900
# fakeram45_128x256 snapHeight_nm = 223900
{
# The process node. This is used to tell cacti what technology to use when
Expand Down Expand Up @@ -61,12 +62,16 @@
{"name": "fakeram45_64x7", "width": 7, "depth": 64, "banks": 1},
{"name": "fakeram45_64x15", "width": 15, "depth": 64, "banks": 1},
{"name": "fakeram45_64x21", "width": 21, "depth": 64, "banks": 1},
{"name": "fakeram45_64x25", "width": 25, "depth": 64, "banks": 1},
{"name": "fakeram45_64x28", "width": 28, "depth": 64, "banks": 1},
{"name": "fakeram45_64x32", "width": 32, "depth": 64, "banks": 1},
{"name": "fakeram45_64x62", "width": 62, "depth": 64, "banks": 1},
{"name": "fakeram45_64x64", "width": 64, "depth": 64, "banks": 1},
{"name": "fakeram45_64x96", "width": 96, "depth": 64, "banks": 1},
{"name": "fakeram45_64x124", "width": 124, "depth": 64, "banks": 1},
{"name": "fakeram45_64x256", "width": 256, "depth": 64, "banks": 1},
{"name": "fakeram45_128x32", "width": 32, "depth": 128, "banks": 1},
{"name": "fakeram45_128x64", "width": 64, "depth": 128, "banks": 1},
{"name": "fakeram45_128x116", "width": 116, "depth": 128, "banks": 1},
{"name": "fakeram45_128x256", "width": 256, "depth": 128, "banks": 1},
{"name": "fakeram45_256x16", "width": 16, "depth": 256, "banks": 1},
Expand Down
1 change: 1 addition & 0 deletions flow/platforms/nangate45/fakeram.tcl
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Expand Up @@ -5,6 +5,7 @@ set design_rams {
black_parrot {64x7 64x96 512x64 256x95 64x15}
bp_multi_top {64x7 32x64 64x96 512x64 256x96 64x15}
bp_fe_top {64x7 64x96 512x64}
cva6 {64x25 64x28 64x256 128x64}
}

set results_dir "~/import/fakeram/results"
Expand Down
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