This project implements a 32-bit RISC-V single-stage core interpreter. It simulates the execution of RISC-V instructions using an instruction memory, data memory, and register file. The program processes multiple test cases, executes instructions, and outputs the results, including performance metrics.
- Instruction Memory: Reads and decodes RISC-V instructions from
imem.txt. - Data Memory: Reads and writes data to
dmem.txtduring instruction execution. - Register File: Simulates 32 general-purpose registers for the RISC-V architecture.
- Instruction Types Supported:
- R-Type:
ADD,SUB,XOR,OR,AND - I-Type:
ADDI,XORI,ORI,ANDI,LW - S-Type:
SW - SB-Type:
BEQ,BNE - UJ-Type:
JAL - HALT
- R-Type:
- Performance Metrics: Calculates and outputs:
- Number of instructions executed
- Number of cycles taken
- Cycles per instruction (CPI)
- Instructions per cycle (IPC)
Bin2ASM-RV/
├── code/
│ ├── input/
│ │ ├── testcase0/
│ │ │ ├── imem.txt
│ │ │ ├── dmem.txt
│ │ ├── testcase1/
│ │ │ ├── imem.txt
│ │ │ ├── dmem.txt
│ │ ├── testcase2/
│ │ ├──├── imem.txt
│ │ ├──├── dmem.txt
│ ├── main.py
├── submissions/
│ ├── output/
│ │ ├── testcase0/
│ │ │ ├── imem.txt
│ │ │ ├── dmem.txt
│ │ ├── testcase1/
│ │ │ ├── imem.txt
│ │ │ ├── dmem.txt
│ │ ├── testcase2/
│ │ ├──├── imem.txt
│ │ ├──├── dmem.txt
├── README.md
- Python 3.6 or higher
- No external dependencies are required.
- Clone the repository:
git clone <repository-url> cd Bin2ASM-RV
- Run the program:
python3 main.py --iodir /{project-directory}/input/ - The program will process all test cases (testcase0, testcase1, testcase2) and generate output files in their respective directories.
For each test case, the following output files are generated:
-
StateResult_SS.txt: State of the core after each cycle.
-
RFResult.txt: Final state of the register file.
-
SS_DMEMResult.txt: Final state of the data memory.
-
PerformanceMetrics_Result.txt: Performance metrics for the test case.