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arch/risc-v/espressif: pick oneshot TIMG from SoC instance count - #20189

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xiaoxiang781216 merged 1 commit into
apache:masterfrom
wmrsouza:feature/oneshot-from-last-timg
Sep 19, 2026
Merged

xiaoxiang781216 merged 1 commit into
apache:masterfrom
wmrsouza:feature/oneshot-from-last-timg

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Summary

Some RISC-V ESP32 SoCs have only a single timer group. The oneshot driver previously hardcoded GROUP_ID to 1 (Timer 0 of Timer Group 1), which overflows soc_timg_gptimer_signals and crashes in periph_rcc_acquire_enter on chips such as ESP32-C2.

This change binds oneshot to the last timer group with TIMG_LL_GET(INST_NUM) - 1, and compiles the GPTIMER group 1 lower-half only when TIMG_LL_GET(INST_NUM) > 1.

Impact

Impact on user: No.

Impact on build: No.

Impact on hardware: No.

Impact on documentation: No.

Impact on security: No.

Impact on compatibility: No.

Testing

Building

make distclean && ./tools/configure.sh -S esp8684-devkitm:timers && make -j && make flash ESPTOOL_PORT=/dev/ttyUSB0 && picocom -b 115200 /dev/ttyUSB0

Running

nsh> oneshot

Results

Opening /dev/oneshot
Maximum delay is 18446744073709551615
Starting oneshot timer with delay 2000000 microseconds
Waiting...
Finished

@github-actions github-actions Bot added Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small labels Sep 18, 2026
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github-actions Bot commented Sep 18, 2026

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MemBrowse Memory Report

No memory changes detected for:

Some SoCs have a single timer group, so a hardcoded GROUP_ID of 1
overflowed soc_timg_gptimer_signals and crashed in
periph_rcc_acquire_enter. Guard gptimer group 1 behind
TIMG_LL_GET(INST_NUM) as well.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
@wmrsouza
wmrsouza force-pushed the feature/oneshot-from-last-timg branch from c40bc55 to 05253ad Compare September 18, 2026 19:00
@xiaoxiang781216
xiaoxiang781216 merged commit 80ccc5d into apache:master Sep 19, 2026
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Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small

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3 participants