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designs/nangate45/tinyRocket/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__tns | -17.1 | -19.0 | Failing | | globalroute__timing__setup__tns | -30.0 | -35.3 | Failing | | finish__timing__setup__tns | -28.5 | -31.9 | Failing | designs/asap7/aes-block/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__tns | -3710.0 | -5150.0 | Failing | | globalroute__timing__setup__tns | -3650.0 | -4295.0 | Failing | | globalroute__timing__hold__ws | -22.5 | -25.9 | Failing | designs/nangate45/ariane133/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__timing__setup__tns | -583.0 | -642.0 | Failing | designs/nangate45/bp_fe_top/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__hold__ws | 0.0 | -0.002 | Failing | | finish__timing__hold__tns | 0.0 | -0.003 | Failing | designs/nangate45/bp_multi_top/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | finish__timing__setup__tns | -262.0 | -291.0 | Failing | designs/sky130hd/chameleon/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__antenna_diodes_count | 188 | 218 | Failing | designs/sky130hd/microwatt/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__tns | -300.0 | -352.0 | Failing | | detailedroute__antenna__violating__nets | 3 | 6 | Failing | Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
designs/rapidus2hp/cva6/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__ws | -0.138 | -0.101 | Tighten | | cts__timing__setup__tns | -287.0 | -205.0 | Tighten | | globalroute__timing__setup__tns | -575.0 | -584.0 | Failing | | finish__timing__setup__tns | -575.0 | -584.0 | Failing | designs/rapidus2hp/cva6/rules-verific.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__ws | -0.157 | -0.14 | Tighten | | cts__timing__setup__tns | -518.0 | -412.0 | Tighten | | globalroute__timing__setup__tns | -650.0 | -697.0 | Failing | | finish__timing__setup__tns | -650.0 | -697.0 | Failing | designs/rapidus2hp/hercules_is_int/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__timing__setup__ws | -0.105 | -0.104 | Tighten | | globalroute__timing__setup__tns | -907.0 | -1120.0 | Failing | | finish__timing__setup__ws | -0.105 | -0.104 | Tighten | | finish__timing__setup__tns | -907.0 | -1120.0 | Failing | Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
designs/sky130hd/microwatt/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__ws | -2.6 | -2.1 | Tighten | | cts__timing__setup__tns | -352 | -224.0 | Tighten | | globalroute__antenna_diodes_count | 2531 | 1962 | Tighten | | globalroute__timing__setup__ws | -2.59 | -2.2 | Tighten | | globalroute__timing__setup__tns | -304.0 | -188.0 | Tighten | | detailedroute__antenna_diodes_count | 2337 | 2377 | Failing | | finish__timing__setup__ws | -2.22 | -1.38 | Tighten | | finish__timing__setup__tns | -183.0 | -30.8 | Tighten | | finish__timing__hold__tns | -46.5 | -18.9 | Tighten | designs/rapidus2hp/hercules_idecode/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | globalroute__timing__setup__ws | -0.0792 | -0.0767 | Tighten | | globalroute__timing__setup__tns | -272.0 | -206.0 | Tighten | | finish__timing__setup__ws | -0.0792 | -0.0767 | Tighten | | finish__timing__setup__tns | -272.0 | -206.0 | Tighten | designs/rapidus2hp/hercules_idecode/rules-verific.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__setup__ws | -0.0226 | -0.0456 | Failing | | cts__timing__setup__tns | -7.13 | -70.6 | Failing | | globalroute__timing__setup__ws | -0.0668 | -0.0831 | Failing | | globalroute__timing__setup__tns | -189.0 | -263.0 | Failing | | finish__timing__setup__ws | -0.0668 | -0.0831 | Failing | | finish__timing__setup__tns | -189.0 | -263.0 | Failing | Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update 3 metrics that consistently fail across CI builds The-OpenROAD-Project#11 and The-OpenROAD-Project#12: - cts__timing__setup__tns: -132.0 -> -156.0 (observed: -141.74) - globalroute__timing__setup__ws: -0.103 -> -0.134 (observed: -0.1216) - finish__timing__setup__ws: -0.103 -> -0.134 (observed: -0.1216) Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
…t-staging/secure-fix-insert-buffer-name-collision Bump OR - fix createNewFlatNet flat/modnet name collision with BTerm
…t-staging/pdk-0.3s-config-changes Changes to Rapidus design configs for PDK 0.3s
When using the slang HDL frontend, macros defined in ADDITIONAL_LIBS
liberty files were not automatically blackboxed. If the same module
had a competing Verilog definition in the source files, slang would
elaborate the Verilog version instead of using the liberty view.
Fix by extracting cell names from ADDITIONAL_LIBS and passing them
as --blackboxed-module arguments to slang, making the behavior
consistent with the builtin Verilog frontend.
Tested:
asap7/uart with a fake ADDITIONAL_LIBS containing uart_tx:
Confirmed slang blackboxes uart_tx from the liberty file
instead of elaborating it from the Verilog source.
asap7/cva6 (which uses slang and ADDITIONAL_LIBS with fakeram
macros that also have .sv definitions in VERILOG_FILES):
make DESIGN_CONFIG=designs/asap7/cva6/config.mk do-yosys-canonicalize
Passes in ~5s with no errors.
asap7/uart without ADDITIONAL_LIBS:
Normal synthesis still passes (no regression).
Fixes The-OpenROAD-Project#3849
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Signed-off-by: Martin Povišer <povik@cutebit.org>
Call report_layer_rc in floorplan.tcl to log per-layer resistance and capacitance values. Placed alongside existing report_units calls since RC values are static across all flow stages. Resolves The-OpenROAD-Project#2841 Signed-off-by: Pavan kumar <pavan@kali.kali.edu>
kepler-formal is primarily an OpenROAD/ORFS developer tool. End-users would typically run LEC transactionally at project completion, not in every CI run. Default LEC_CHECK to 0 when kepler-formal is not present to avoid hard failures in environments where it is not installed. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Signed-off-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Signed-off-by: Augusto Berndt <augusto.berndt@precisioninno.com>
…t-staging/secure-gpl-fix-incremental update metrics for gpl incremental fix
Signed-off-by: Dhirenderchoudhary <dhirenderchoudhary0001@gmail.com>
Signed-off-by: Dhirenderchoudhary <dhirenderchoudhary0001@gmail.com>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
…ec-optinal flow: only enable LEC_CHECK when kepler-formal is installed
…ON=25, PLACE_DENSITY=0.70, clk_period=1800) Signed-off-by: Jorge Ferreira <jorge.ferreira@precisioninno.com>
…f-by: Dhirenderchoudhary Signed-off-by: Dhirenderchoudhary <dhirenderchoudhary0001@gmail.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
…fix/genmetrics-fd-leaks fix: use context managers to prevent file descriptor leaks in genMetrics.py
…t-staging/work-home test: consider WORK_HOME
Signed-off-by: Cho Moon <cmoon@precisioninno.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
…t-staging/pip-ubuntu24 etc: install pip packages on ubuntu24+
The hardcoded relative path `designs/src/mock-array/util.tcl` breaks when the working directory isn't the repo root. Use $::env(DESIGN_HOME) which is the standard pattern for all other SDC files. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Use $(PLATFORM_DIR) consistently instead of hardcoded
./platforms/$(PLATFORM). Fix lib path from $(LIB_DIR)/fakeram7_256x32.lib
to $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x32.lib to match the actual
directory structure:
$ find . | grep fakeram7_256x32\.lib
./platforms/asap7/lib/NLDM/fakeram7_256x32.lib
$
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
One-off ad-hoc plotting script for some discussion post, not since maintained. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Some ad hoc testing scripts These utility scripts are not referenced anywhere in the codebase. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
…t-staging/fix-4075 build: use deps prefixes
Signed-off-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
…t-staging/enable-4-mod-swap enable mod swap for 3 more designs
…tency fix: use portable path in mock-cpu constraint.sdc
…-script Remove unused plot-area-min-clock-period.py
…anup Remove unused plot_congestion.py and plot_floorplan.py
…nsistency fix: standardize paths in asap7 riscv32i config.mk
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
…t-staging/docker-verific docker: add optioin for verific
Signed-off-by: Vitor Bandeira <vvbandeira@precisioninno.com>
…t-staging/new-ci ci: move to new version
…owatt DESIGN_DIR is already defined in the Makefile as $(dir $(DESIGN_CONFIG)). These two designs defined redundant custom variables (chameleon_DIR, microwatt_DIR) that were identical to DESIGN_DIR. Use the standard variable to simplify config and remove non-standard patterns. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
$(dir ...) in GNU Make always appends a trailing slash, so DESIGN_DIR ended up as e.g. ".../chameleon/". When config.mk files use $(DESIGN_DIR)/gds/file.gds, this produced paths with "//" instead of "/". Mind-bogglingly, this was the only difference we could find that caused CI metric failures (antenna_diodes_count) in PR The-OpenROAD-Project#4080. Strip the trailing slash with $(patsubst %/,%,...) so that replacing custom _DIR variables with DESIGN_DIR is a true no-op. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Remove design BUILD.bazel files that are being replaced by auto-generated targets from the orfs_design() macro in bazel-orfs. Also remove stale merge_lib.py/preprocessLib.py references from flow/util/BUILD.bazel (files were deleted in 644ff70 but the BUILD reference was not updated). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
…consistency fix: use DESIGN_DIR instead of custom dir variables in chameleon/microwatt
…gn-build-files build: remove hand-written design BUILD files and stale references
Signed-off-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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