[UR][HIP] Implement USM memory pool experimental API#22673
Open
zjin-lcf wants to merge 2 commits into
Open
Conversation
Port the CUDA adapter's stream-ordered (async) allocation support to HIP. urEnqueueUSMDeviceAllocExp and urEnqueueUSMFreeExp are implemented using the HIP stream-ordered memory allocator (hipMallocAsync/hipFreeAsync) on the device's default memory pool, mirroring the CUDA implementation but using ScopedDevice instead of ScopedContext. Host and shared async allocations remain unsupported, matching CUDA. Register the four async-alloc entry points in the adapter's urGetEnqueueExpProcAddrTable; they were previously stubbed but never wired into the DDI table, so the loader returned UR_RESULT_ERROR_UNINITIALIZED. UR_DEVICE_INFO_ASYNC_USM_ALLOCATIONS_SUPPORT_EXP now queries hipDeviceAttributeMemoryPoolsSupported so the device advertises the ext_oneapi_async_memory_alloc aspect when supported. The default-pool async allocation e2e tests (async_alloc, ooo_queue_async_alloc) pass on an AMD Instinct MI300A (gfx942). Tests that construct a sycl memory_pool still require the USM memory pool experimental API (urUSMPool*Exp), which remains unimplemented on HIP. Co-authored-by: Cursor <cursoragent@cursor.com>
Port the CUDA adapter's native USM memory pool support to HIP, backed by the HIP stream-ordered memory allocator (hipMemPool_t). A ur_usm_pool_handle_t may now wrap either a UMF pool (existing behaviour) or a native hipMemPool_t. Implement the experimental pool entry points: urUSMPoolCreateExp, urUSMPoolDestroyExp, urUSMPoolGetDefaultDevicePoolExp, urUSMPoolGetInfoExp, urUSMPoolSetInfoExp and urUSMPoolTrimToExp using hipMemPoolCreate/Destroy, hipDeviceGetDefaultMemPool, hipMemPoolGet/SetAttribute and hipMemPoolTrimTo. urUSMPoolGetDevicePoolExp and urUSMPoolSetDevicePoolExp remain unsupported, matching CUDA. urEnqueueUSMDeviceAllocExp now allocates from the supplied native pool via hipMallocFromPoolAsync when a pool is provided, falling back to the device's default pool otherwise. The USM memory pool e2e tests (memory_pool, async_alloc_from_pool, async_alloc_from_default_pool, ooo_queue_async_alloc_from_pool) pass on an AMD Instinct MI300A (gfx942). Co-authored-by: Cursor <cursoragent@cursor.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Ports the CUDA adapter's native USM memory pool experimental API to the HIP adapter, backed by the HIP stream-ordered memory allocator (
hipMemPool_t).ur_usm_pool_handle_tcan now wrap either a UMF pool (existing behaviour) or a nativehipMemPool_t.urUSMPoolCreateExp,urUSMPoolDestroyExp,urUSMPoolGetDefaultDevicePoolExp,urUSMPoolGetInfoExp,urUSMPoolSetInfoExpandurUSMPoolTrimToExpusinghipMemPoolCreate/hipMemPoolDestroy,hipDeviceGetDefaultMemPool,hipMemPoolGet/SetAttributeandhipMemPoolTrimTo.urUSMPoolGetDevicePoolExp/urUSMPoolSetDevicePoolExpremain unsupported, matching CUDA.urEnqueueUSMDeviceAllocExpnow allocates from the supplied native pool viahipMallocFromPoolAsync, falling back to the device's default pool otherwise.Dependency
This PR is stacked on #22672 ([UR][HIP] Implement async device allocation). Until that PR merges, the diff here also contains its commit; the only commit for review in this PR is
[UR][HIP] Implement USM memory pool experimental API. Please merge #22672 first; this branch will be rebased ontosyclafterwards.Test plan
The USM memory pool e2e tests pass on an AMD Instinct MI300A (gfx942):
AsyncAlloc/device/memory_pool.cppAsyncAlloc/device/async_alloc_from_pool.cppAsyncAlloc/device/async_alloc_from_default_pool.cppAsyncAlloc/device/ooo_queue_async_alloc_from_pool.cpp