decoder: Ensure safe handling of illegal instructions by blocking all side effects

[Anubhav-30]

This change strengthens the handling of illegal instructions in the decoder
by ensuring that no unintended side effects are triggered when an illegal
instruction is detected.

In addition to disabling write and control signals, this update explicitly:

• disables register read enables (rf_ren_a_o, rf_ren_b_o)
• blocks instruction cache invalidation (icache_inval_o)
• forces CSR operations to a safe read-only mode

This prevents any unintended data access, control flow changes, or CSR
side effects from occurring due to partially decoded illegal instructions.

The change is non-intrusive and aligns with safe CPU design practices,
ensuring that illegal instructions are fully contained within the decoder
stage without affecting downstream pipeline behavior.

[SamuelRiedel]

This PR gates signals that do not actually produce any architectural side effects.

We are closing this PR as the proposed changes do not align with our current development priorities, address any tracked issues, or meet our required technical standards.