[HLSL] Add LinAlg accumulation contention coverage

[JoeCitizen]

Summary

• extend the descriptor, group-shared and vector accumulation harnesses to drive deterministic contention from multiple Waves, threads and dispatch groups while preserving the existing single-invocation defaults
• add a guarded F32 descriptor case with two Waves in each of two thread groups; four exactly representable 0.5 additions to initial 1.0 produce the unique exact result 3.0
• add a guarded F16 group-shared case with two Waves contending in one thread group and a guarded F16 vector case with eight threads in each of two thread groups
• retain capability-gated I32 descriptor-matrix, group-shared-matrix and descriptor-vector cases for implementations that advertise integer atomic support
• add a checked host oracle for repeated integer accumulation totals and a host self-test

The runnable F16/F32 controls ensure every destination path executes locally. The I32 cases are not success-shaped fallbacks: they remain selected only when the runtime reports the matching atomic destination support.

Validation

• built the Release ExecHLSLTests target
• compiled LinAlgTests.cpp directly against the preview D3D12 headers
• ran the 14-case accumulation selection with the ABI-corrected disposable WARP: 11 passed and the 3 I32 capability cases skipped because WARP reports both integer atomic destinations unsupported
• positively executed the F32 descriptor and F16 group-shared contention cases on unmodified public preview WARP
• positively executed the F16 vector contention case, plus all three existing vector accumulation regressions, on the disposable WARP decoder corrected for current handle-first DXIL operands
• reran the capability-policy host test and the non-accumulating descriptor round-trip regression
• inspected emitted DXIL for exact wave size 4, two active Waves, Wave-scope Accumulator matrices, guarded descriptor offsets/strides, group-shared addrspace(3) accumulation, eight-thread dispatches and handle-first vector operands
• clang-format 17.0.1, git diff --check and a focused graphics correctness review pass

Runtime compatibility notes

WARP advertises MatrixConstruction for I32 but reports UAV=0 and groupshared=0 for I32 AtomicAccumulateStore, so those three cases correctly report NotApplicable. Public preview WARP also retains the known obsolete vector-first VectorAccumulate decoder; vector execution used the previously documented disposable decoder correction. No runtime change is included here.

No physical GPU or packaged-HLK qualification is claimed.

Stack

This draft is stacked on PR #8675, which is stacked on PR #8674, PR #8673, PR #8672, PR #8671, PR #8670, PR #8669, PR #8668, PR #8667, PR #8666, PR #8665 and PR #8662. Until those ancestors land, this diff contains their commits as well. The contention change itself is commit 964c0f316.

This remains a draft for named human review. The reviewer should verify the atomic invocation counts, uniform Wave participation, group-shared barriers, exact/order-independent value choices, destination guards, capability gating and checked host totals before requesting maintainer review.

Refs #7841
Refs #8561
Refs #8562
Refs #8565
Refs #8654

Assisted-by: GitHub Copilot