Add support for Qualcomm TSCSS hardware

Documentation/devicetree/bindings/ptp/qcom,tsc.yaml

@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/qcom,tsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Timestamp Counter Subsystem (TSCSS)
+
+maintainers:
+  - Imran Shaik <imran.shaik@oss.qualcomm.com>
+  - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description:
+  Qualcomm TSCSS is a time synchronization subsystem composed of two main
+  blocks - the Time Stamp Counter (TSC) and the Event Timestamp Unit (ETU).
+
+  The TSC block is a timestamp generator that maintains a running counter used
+  for system timekeeping. The ETU block captures timestamps for external events
+  using one of the available timestamp sources.
+
+properties:
+  compatible:
+    enum:
+      - qcom,tsc
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: tsc
+      - const: etu
+
+  clocks:
+    items:
+      - description: TSC AHB clock
+      - description: TSC cntr clock
+      - description: TSC ETU clock
+
+  clock-names:
+    items:
+      - const: cfg_ahb
+      - const: cntr
+      - const: etu
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    items:
+      - const: etu_summary_irq
+
+  qcom,tsc-nsec-update:
+    description:
+      Indicates the TSC counters have values in nanoseconds, rather than
+      in secs and nanoseconds.
+    type: boolean
+
+  qcom,etu-slice:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      Array of ETU slice numbers corresponding to the ETU sel.
+      In case this property is not defined the sel number will be
+      considered as the slice number for ETU offset calculation.
+
+  qcom,etu-event-sel:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      Array of ETU event sel numbers for the corresponding ETU slice
+      numbers.
+
+  qcom,etu-event-names:
+    $ref: /schemas/types.yaml#/definitions/string-array
+    description:
+      ETU event sel names for the corresponding event sel numbers.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - interrupt-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    tsc: tsc@1c80000 {
+      compatible = "qcom,tsc";
+      reg = <0x01c80000 0x2000>,
+            <0x01ca0000 0x20000>;
+      reg-names = "tsc", "etu";
+      clocks = <&tscss_ahb_clock>, <&tscss_cntr_clock>,
+               <&tscss_cntr_clock>;
+      clock-names = "cfg_ahb", "cntr", "etu";
+      interrupts = <GIC_SPI 766 IRQ_TYPE_EDGE_RISING>;
+      interrupt-names = "etu_summary_irq";
+      qcom,etu-slice = <10 11>;
+      qcom,etu-event-sel = <10 11>;
+      qcom,etu-event-names = "gps_pps", "tod_pps";
+      qcom,tsc-nsec-update;
+    };

arch/arm64/boot/dts/qcom/lemans.dtsi

@@ -5660,6 +5660,14 @@
 				bias-disable;
 			};
 
+			/* CCI async input GPIOs */
+			cci_async_default: cci-async-state {
+				pins = "gpio68", "gpio69";
+				function = "cci_async";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
 			cci0_0_default: cci0-0-default-state {
 				pins = "gpio60", "gpio61";
 				function = "cci_i2c";
@@ -9237,4 +9245,32 @@
 
 		status = "disabled";
 	};
+
+	tsc@1c80000 {
+		compatible = "qcom,tsc";
+		reg = <0x0 0x01c80000 0x0 0x2000>,
+		      <0x0 0x01c90000 0x0 0x10000>;
+		reg-names = "tsc", "etu";
+
+		clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+			 <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+			 <&gcc GCC_TSCSS_ETU_CLK>;
+		clock-names = "cfg_ahb", "cntr", "etu";
+
+		assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+				  <&gcc GCC_TSCSS_ETU_CLK>;
+		assigned-clock-rates = <15625000>, <15625000>;
+
+		qcom,tsc-nsec-update;
+
+		interrupts = <GIC_SPI 766 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "etu_summary_irq";
+
+		qcom,etu-slice = <10 11>;
+		qcom,etu-event-sel = <10 11>;
+		qcom,etu-event-names = "gps_pps", "tod_pps";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&cci_async_default>;
+	};
 };

arch/arm64/configs/qcom.config

@@ -45,6 +45,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0
 CONFIG_PM=y
 CONFIG_POWERCAP=y
 CONFIG_PROC_EVENTS=y
+CONFIG_PTP_QCOM_CLOCK_TSC=m
 CONFIG_QCA808X_PHY=m
 CONFIG_QCOM_QMI_COOLING=y
 CONFIG_REMOTEPROC_THERMAL=y

drivers/ptp/Kconfig

@@ -263,4 +263,13 @@ config PTP_NETC_V4_TIMER
 	  synchronization. It also supports periodic output signal (e.g. PPS)
 	  and external trigger timestamping.
 
+config PTP_QCOM_CLOCK_TSC
+	tristate "Qualcomm TSC as PTP clock"
+	depends on COMMON_CLK && PTP_1588_CLOCK
+	help
+	  This driver adds support for using the Qualcomm Timestamp Counter (TSC)
+	  as a PTP clock the requires for time stamping of PTP packets.
+	  It also registers interrupts for Event Timestamp Unit (ETU) and updates
+	  the TSC timestamps to PTP clock event.
+
 endmenu

drivers/ptp/Makefile

@@ -22,3 +22,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_OCP)	+= ptp_ocp.o
 obj-$(CONFIG_PTP_DFL_TOD)		+= ptp_dfl_tod.o
 obj-$(CONFIG_PTP_S390)			+= ptp_s390.o
 obj-$(CONFIG_PTP_NETC_V4_TIMER)		+= ptp_netc.o
+obj-$(CONFIG_PTP_QCOM_CLOCK_TSC)	+= ptp_qcom_tsc.o