c-variadic: support ppcf128 by folkertdev · Pull Request #164004 · rust-lang/rust

folkertdev · 2026-10-08T19:49:00Z

On powerpc64 this needs a change to lower the alignment of ppcf128 to only 8 when read from a VaList.

On powerpc this needs some additional changes to the logic to match GCC. Of course, in clang the ABI of this type is completely broken, we'll see if my fix for that gets merged llvm/llvm-project#225956.

folkertdev · 2026-10-08T19:49:38Z

+    // POWERPC: stwu 1, -32(1)
+    // POWERPC: lbz 5, 1(3)
+    // POWERPC-NEXT: cmplwi 5, 6
+    // POWERPC-NEXT: bgt 0, .LBB3_2
+    // POWERPC-NEXT: lwz 4, 8(3)
+    // POWERPC-NEXT: rlwinm 6, 5, 3, 24, 28
+    // POWERPC-NEXT: addi 5, 5, 2
+    // POWERPC-NEXT: add 4, 4, 6
+    // POWERPC-NEXT: addi 4, 4, 32
+    // POWERPC-NEXT: b .LBB3_3
+    // POWERPC-NEXT: .LBB3_2:
+    // POWERPC-NEXT: lwz 4, 4(3)
+    // POWERPC-NEXT: addi 4, 4, 7
+    // POWERPC-NEXT: rlwinm 4, 4, 0, 0, 28
+    // POWERPC-NEXT: addi 5, 4, 16
+    // POWERPC-NEXT: stw 5, 4(3)
+    // POWERPC-NEXT: li 5, 8
+    // POWERPC-NEXT: .LBB3_3:
+    // POWERPC-NEXT: lwz 6, 4(4)
+    // POWERPC-NEXT: stb 5, 1(3)
+    // POWERPC-NEXT: stw 6, 28(1)
+    // POWERPC-NEXT: lwz 3, 0(4)
+    // POWERPC-NEXT: stw 3, 24(1)
+    // POWERPC-NEXT: lwz 3, 12(4)
+    // POWERPC-NEXT: lfd 1, 24(1)
+    // POWERPC-NEXT: stw 3, 20(1)
+    // POWERPC-NEXT: lwz 3, 8(4)
+    // POWERPC-NEXT: stw 3, 16(1)
+    // POWERPC-NEXT: lfd 2, 16(1)
+    // POWERPC-NEXT: addi 1, 1, 32


LLVM does a poor job here, GCC produces way fewer instructions https://godbolt.org/z/4xE4e9f5d.

View changes since the review

folkertdev · 2026-10-09T07:22:47Z

r? beetrees
cc @tgross35

I've tested this with abi-cafe. Testing e.g. with the roundtrip test we have is inconvenient because we currently don't have any constructors.

beetrees

The 32-bit soft-float case isn't quite right, but the hard-float case LGTM. For the rountrip test, couldn't we use transmute for now and leave a FIXME to replace with from_components once #164021 is merged?

View changes since this review

beetrees · 2026-10-15T17:12:06Z


    // "Align" the register count when the type is passed as `i64`.
-    if is_i64 || (is_f64 && is_soft_float_abi) {
+    if is_i64 || ((is_f64 || is_ppcf128) && is_soft_float_abi) {


The ABI spec says that QUAD_GP (which is what ppcf128 falls into on soft float) is not aligned when passed in registers.

I think that means we can read it as 2 f64 values? Because if it's not aligned it might be split between gpr and the overflow_arg_area?

It's not aligned, but if there aren't 4 available GPRs the whole thing is passed in the overflow area. It's the same concept as passing it in FPRs, just with 4 registers instead of 2.

Suggested change

if is_i64 || ((is_f64 || is_ppcf128) && is_soft_float_abi) {

if is_i64 || (is_f64 && is_soft_float_abi) {

Since we're leaving soft-float support for later and this is against the specification, may as well not add is_ppcf128 here.

beetrees · 2026-10-15T17:35:01Z

                Float::F16 | Float::F16B | Float::F32 => unreachable!(),
-                Float::F64 | Float::F128 | Float::PpcF128 => { /* fall through */ }
+                Float::F64 | Float::F128 => { /* fall through */ }
+                Float::PpcF128 => return Align::EIGHT,


Per the ABI spec, on soft float ppcf128 arguments are only passed with an alignment of 4. 8 is correct for hard float.

I suspect we'll just read it as two f64 values

rustbot · 2026-10-15T18:01:29Z

Reminder, once the PR becomes ready for a review, use @rustbot ready.

folkertdev · 2026-10-15T23:29:07Z

We don't actually support any true softfloat targets (and the va_arg logic asserts this). We do have spe targets though, which are (from what I understand) kinda softfloat, but maybe not entirely?

So, I guess we try to properly support spe now? Those targets are extremely tier 3 though. I'd kinda rather do it as a follow-up?

beetrees · 2026-10-16T08:41:52Z

Leaving soft-float for later is fine - just leave a FIXME for it next to the assert!(!is_soft_float_abi);.

folkertdev

We don't even have PartialEq for the type right now. We'll definitely come back to it when adding c_longdouble.

@rustbot ready

View changes since this review

folkertdev · 2026-10-16T09:11:44Z

                Float::F16 | Float::F16B | Float::F32 => unreachable!(),
-                Float::F64 | Float::F128 | Float::PpcF128 => { /* fall through */ }
+                Float::F64 | Float::F128 => { /* fall through */ }
+                Float::PpcF128 => return Align::EIGHT,


I suspect we'll just read it as two f64 values

beetrees

Since we're leaving the roundtrip test for later, could you add a FIXME in tests/ui/c-variadic/roundtrip.rs for testing ppcf128<->__ibm128. Otherwise just two things:

View changes since this review

beetrees · 2026-10-16T21:55:52Z


    // "Align" the register count when the type is passed as `i64`.
-    if is_i64 || (is_f64 && is_soft_float_abi) {
+    if is_i64 || ((is_f64 || is_ppcf128) && is_soft_float_abi) {


Suggested change

if is_i64 || ((is_f64 || is_ppcf128) && is_soft_float_abi) {

if is_i64 || (is_f64 && is_soft_float_abi) {

Since we're leaving soft-float support for later and this is against the specification, may as well not add is_ppcf128 here.

folkertdev · 2026-10-17T12:14:13Z

@rustbot ready

folkertdev

Sorry about that, that's what I get for doing it manually instead of copying from github.

@rustbot ready

View changes since this review

folkertdev · 2026-10-17T15:50:44Z

    let max_regs = 8u8;
-    let use_regs = bx.icmp(IntPredicate::IntULT, num_regs, bx.const_u8(max_regs));
+    let reg_size = if is_passed_in_fprs { 8 } else { 4 };
+    let reg_incr = layout.size.bytes().div_ceil(u64::from(reg_size)) as u8;


I went with naming it reg_incr because we already have num_regs so also having n_reg could cause confusion.

folkertdev · 2026-10-17T16:42:33Z

+    // POWERPC-NEXT: .LBB2_2:
+    // POWERPC-NEXT: lwz 3, 4(5)
+    // POWERPC-NEXT: li 6, 8
+    // POWERPC-NEXT: addi 3, 3, 7
+    // POWERPC-NEXT: rlwinm 4, 3, 0, 0, 28
+    // POWERPC-NEXT: addi 3, 4, 8
+    // POWERPC-NEXT: stw 3, 4(5)
+    // POWERPC-NEXT: lwz 3, 0(4)
+    // POWERPC-NEXT: lwz 4, 4(4)
+    // POWERPC-NEXT: stb 6, 0(5)
+    // POWERPC-NEXT: blr


I noticed some check lines were missing

folkertdev · 2026-10-17T16:45:34Z

-    // POWERPC-NEXT: clrlwi 4, 3, 24
-    // POWERPC-NEXT: cmplwi 4, 7
+    // POWERPC-NEXT: rlwinm 4, 3, 0, 24, 30
+    // POWERPC-NEXT: cmplwi 4, 6
    // POWERPC-NEXT: bgt 0, .LBB2_2
    // POWERPC-NEXT: lwz 4, 8(5)
-    // POWERPC-NEXT: rlwinm 6, 3, 0, 29, 30
-    // POWERPC-NEXT: rlwinm 3, 3, 2, 27, 28
+    // POWERPC-NEXT: rlwinm 6, 3, 0, 0, 30
+    // POWERPC-NEXT: rlwinm 3, 3, 2, 24, 28


The assembly changed a bit here, but I believe this is equivalent in practice. At least, the code seems correct, abi-cafe is happy, so this must be right. This is slightly different from clang/gcc though

https://godbolt.org/z/PqahaPhzo

beetrees

LGTM

@bors r+ rollup

View changes since this review

rust-bors · 2026-10-17T17:14:57Z

📌 Commit 24f5f82 has been tentatively approved by beetrees

It will be put into the queue for this repository once PR CI succeeds.

rust-bors · 2026-10-18T02:08:00Z

☀️ Test successful - CI
Approved by: beetrees
Duration: 3h 19m 29s
Pushing 02fb0a1 to main...

github-actions · 2026-10-18T02:10:57Z

What is this?

This is an experimental post-merge analysis report that shows differences in test outcomes between the merged PR and its parent PR.

Comparing 8006091 (parent) -> 02fb0a1 (this PR)

Test differences

Show 2 test diffs

2 doctest diffs were found. These are ignored, as they are noisy.

Test dashboard

Run

cargo run --manifest-path src/ci/citool/Cargo.toml -- \
    test-dashboard 02fb0a16311c3411fa373627706da085cd8fbd3c --output-dir test-dashboard

And then open test-dashboard/index.html in your browser to see an overview of all executed tests.

Job duration changes

test-x86_64-mingw-1: 1h 47m -> 3h 18m (+84.9%)
dist-x86_64-msvc-alt: 1h 41m -> 2h 56m (+74.3%)
test-i686-msvc: 1h 33m -> 2h 31m (+62.6%)
dist-armhf-linux: 1h 3m -> 1h 30m (+42.9%)
test-i686-gnu-nopt-1: 2h 22m -> 1h 22m (-42.5%)
test-x86_64-rust-for-linux: 59m 30s -> 34m 32s (-42.0%)
dist-powerpc64-linux-musl: 1h 9m -> 1h 37m (+41.4%)
dist-arm-linux-musl: 1h 17m -> 1h 48m (+40.3%)
dist-x86_64-netbsd: 1h 7m -> 1h 32m (+37.2%)
test-x86_64-gnu-gcc-core-tests: 13m 57s -> 9m 7s (-34.6%)

How to interpret the job duration changes?

Job durations can vary a lot, based on the actual runner instance
that executed the job, system noise, invalidated caches, etc. The table above is provided
mostly for t-infra members, for simpler debugging of potential CI slow-downs.

rust-timer · 2026-10-18T02:55:45Z

Finished benchmarking commit (02fb0a1): comparison URL.

Overall result: ✅ improvements - no action needed

@rustbot label: -perf-regression

Instruction count

Our most reliable metric. Used to determine the overall result above. However, even this metric can be noisy.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	-	-	0
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-0.3%	[-0.5%, -0.0%]	9
All ❌✅ (primary)	-	-	0

Max RSS (memory usage)

Results (secondary 5.0%)

A less reliable metric. May be of interest, but not used to determine the overall result above.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	5.0%	[5.0%, 5.0%]	1
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-	-	0

Cycles

Results (secondary 3.3%)

A less reliable metric. May be of interest, but not used to determine the overall result above.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	3.3%	[3.3%, 3.3%]	1
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-	-	0

Binary size

Results (primary 0.0%, secondary 0.0%)

A less reliable metric. May be of interest, but not used to determine the overall result above.

	mean	range	count
Regressions ❌ (primary)	0.0%	[0.0%, 0.0%]	1
Regressions ❌ (secondary)	0.0%	[0.0%, 0.0%]	1
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	0.0%	[0.0%, 0.0%]	1

Bootstrap: 491.611s -> 489.75s (-0.38%)
Artifact size: 408.96 MiB -> 409.00 MiB (0.01%)

folkertdev added O-PowerPC Target: PowerPC processors F-c_longdouble `#![feature(c_longdouble)]` labels Oct 8, 2026

folkertdev commented Oct 8, 2026

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folkertdev force-pushed the ppcf128-c-variadic branch from 22ec35d to 2d7d726 Compare October 8, 2026 19:59

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folkertdev force-pushed the ppcf128-c-variadic branch from cb3994c to 055d417 Compare October 16, 2026 09:16

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folkertdev force-pushed the ppcf128-c-variadic branch from e21e982 to f851aa9 Compare October 17, 2026 11:47

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Comment thread compiler/rustc_codegen_llvm/src/va_arg.rs Outdated

Comment thread compiler/rustc_codegen_llvm/src/va_arg.rs Outdated

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folkertdev force-pushed the ppcf128-c-variadic branch 2 times, most recently from c441d90 to 8af06b3 Compare October 17, 2026 16:11

c-variadic: support ppcf128

24f5f82

folkertdev force-pushed the ppcf128-c-variadic branch from 8af06b3 to 24f5f82 Compare October 17, 2026 16:36

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rust-bors Bot added merged-by-bors This PR was explicitly merged by bors. and removed S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. labels Oct 18, 2026

rust-bors Bot merged commit 02fb0a1 into rust-lang:main Oct 18, 2026
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rust-bors Bot mentioned this pull request Oct 18, 2026

add core::arch::{x86, x86_64}::x87_f80 #163992

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folkertdev mentioned this pull request Oct 25, 2026

C interop: f80, f128 and c_longdouble rust-lang/goals#701

Open

	if is_i64 \|\| ((is_f64 \|\| is_ppcf128) && is_soft_float_abi) {
	if is_i64 \|\| (is_f64 && is_soft_float_abi) {

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Test differences

Job duration changes

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