A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.
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May 28, 2026 - Verilog
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single-cycle-cpu
Here are 6 public repositories matching this topic...
Single-cycle 32-bit MIPS CPU designed and simulated in Logisim, built for the Computer Architecture Lab (LCOM 3010) at the Islamic University of Gaza. Supports lw, sw, add, sub, and, or, slt, beq, and j.
mips assembly university-project digital-logic computer-architecture logisim digital-design mips-cpu cpu-design single-cycle-cpu
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Jul 25, 2026
CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .
instruction-set-architecture memory-hierarchy verilog-project cache-implementation single-cycle-cpu alu-design computer-architecture-and-assembly-language 8-bit-processor
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Oct 10, 2025 - Verilog
Formally verified, synthesis-ready 8-bit RISC CPU in Verilog. Optimized for efficient hardware implementation.
cpu assembler verilog computer-architecture digital-design logic-design 8-bit-cpu cpu-design custom-cpu single-cycle-cpu digital-design-and-computer-architecture
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Aug 10, 2026 - Verilog
MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy
mips vhdl computer-organization hardware-design multi-cycle-cpu single-cycle-cpu pipelined-processor-design
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Dec 18, 2025 - VHDL
A single-cycle RISC-V CPU implemented in Verilog, with arithmetic, memory, branch, and jump instructions verified using Icarus Verilog and GTKWave.
processor verilog computer-architecture gtkwave risc-v iverilog digital-design rv32i cpu-design hardware-design single-cycle-cpu
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Jun 20, 2026 - Verilog
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