NXP T2080 / CW VPX3-152: VxWorks 7 64-bit boot support

[dgarske]

NXP T2080 / CW VPX3-152: VxWorks 7 64-bit boot support

Adds wolfBoot support for booting VxWorks 7 SMP 64-bit (and signed ELF images) on the NXP T2080 (quad e6500) / Curtiss-Wright VPX3-152, verified booting to the VxWorks shell (CPU Count: 8, Target Name: vxTarget).

Key fix

The e6500 cluster L2 cache must be brought up in a specific order: set L2PE (ECC) in its own write and poll it set BEFORE enabling L2E, with L2FI|L2LFC on the flash-invalidate (the CW/SDK2.0 sequence). wolfBoot previously wrote a bare L2FI then L2E alone, which left the L2 ECC array uninitialized for the kernel's 0x1E0000 set; once ECC checking became active the first instruction fetch there raised an uncorrectable multi-bit ECC machine check (MCSR[IF]=0x10000, L2ERRDET=0x80000080) and VxWorks hung at the MC vector. With the corrected order wolfBoot runs L2 ECC on throughout and the OS inherits a clean, ECC-valid L2.

Fixes

• e6500 cluster-L2 ECC bring-up ordering (the root cause above), in src/boot_ppc_start.S.
• ELF in-place loader staging-overlap: the staging buffer overlapped the ELF load span and the collide-guard silently dropped the segment holding the entry point; staging moved above the segment span + a loud error on overlap.
• 64-bit OS hand-off correctness: LAW/TLB transition to 36-bit physical, IVOR exception vectoring, and MSR state aligned with the CW U-Boot bootm profile.

Features

• Boot VxWorks 7 SMP 64-bit via the ePAPR spin-table protocol, releasing all four cores (CPU Count 8).
• Boot signed ELF images directly (in-place PT_LOAD scatter loader; no uImage repack needed).
• DPAA bring-up: LIODN programming + QMan/BMan software-portal init (required before a DPAA-aware OS).
• Board configs for CW VPX3-152 (256 MB NOR @ 0xF0000000, 4 GB DDR3L) and NAII 68PPC2.

Improvements

• PPC32 printf("%lld") support (PRINTF_LONG_LONG auto-enabled for the PPC toolchain) in src/string.c.
• CI: a T2080 build entry added to .github/workflows/test-configs.yml; T2080 build rules in arch.mk; T2080 target docs in docs/Targets.md.

New build options

• BOARD_CW_VPX3152 / BOARD_NAII_68PPC2 -- select the T2080 board variant (addresses, oscillator, DDR). Default is the T2080 RDB.
• OS_64BIT=1 -- 64-bit OS hand-off (ePAPR/VxWorks 7 64-bit); MSR[CM]=0 at entry, OS self-promotes.
• ELF=1 -- enable the in-place ELF image loader.
• WOLFBOOT_NO_DPAA -- disable DPAA/QMan/BMan init (define to opt out; default is on for T2080).
• WOLFBOOT_EARLY_UART -- compile in the e6500 early-boot UART debug helpers (off by default; OS-porting bring-up aid).

Testing

Cold-boots VxWorks 7 reliably to the SMP shell. No regression to the existing T2080 RDB / NAII paths (board behavior is gated on BOARD_CW_VPX3152).

[Copilot]

Pull request overview

This PR fixes multiple early-boot issues for NXP QorIQ T2080/e6500 targets to enable wolfBoot to boot successfully on the Curtiss‑Wright VPX3‑152 (256 MB NOR @ 0xF0000000, CCSRBAR relocated to 0xEF000000), while keeping NAII 68PPC2 behavior intact.

Changes:

• Corrects high-address loads on e6500 (avoid lis sign-extension) and adjusts TLB1/CCSRBAR relocation sequencing to prevent faults.
• Adds VPX3‑152-specific TLB sizing/mapping changes to avoid TLB multi-hit overlap with 256 MB NOR.
• Updates T2080 HAL for VPX3‑152 constraints (disable MP, guard flash caching paths, DTS address handling) and refreshes DDR configuration constants/docs/CI coverage.

Reviewed changes

Copilot reviewed 6 out of 6 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/boot_ppc_start.S	e6500-safe address loading, CCSRBAR relocation/TLB ordering fixes, VPX3‑152 TLB sizing & flash mapping adjustments, early UART debug helpers
src/boot_ppc_mp.S	Comment/clarity cleanup in MP boot assembly
hal/nxp_t2080.c	VPX3‑152 MP disable guard, flash caching guards, flash bounds checks, DTS NULL for VPX3‑152, minor synchronization improvements
hal/nxp_t2080.h	Updates DDR parameterization and expands MODE3–8 defines; populates additional RDB register values
docs/Targets.md	Expanded T2080 target documentation: board matrix, VPX3‑152 specifics, programming/recovery notes
.github/workflows/test-configs.yml	Adds board-specific build jobs for T2080 variants in CI

Comments suppressed due to low confidence (1)

hal/nxp_t2080.c:400

• hal_flash_enable_caching() is a no-op for BOARD_CW_VPX3152, but the DEBUG_UART log still prints "Flash: caching enabled" unconditionally. This makes UART logs misleading when debugging VPX3-152 boot/flash performance. Gate the log behind the same #ifndef BOARD_CW_VPX3152, or print an alternate message indicating caching is skipped/uncached on this board.

#ifndef BOARD_CW_VPX3152
    /* Rewrite flash TLB entry with cacheable attributes.
     * MAS2_M = memory coherent, enables caching */
    set_tlb(1, 2,
        FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
        FLASH_TLB_PAGESZ, 1);

    /* Invalidate L1 I-cache so new TLB attributes take effect */
    invalidate_icache();
#endif

#ifdef DEBUG_UART
    wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n");
#endif

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[Copilot]

Pull request overview

Copilot reviewed 15 out of 15 changed files in this pull request and generated 7 comments.

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