Skip to content

[stm32n6, stm32h5, eth] Change eth driver to allow the MDIO clock div to be configurable #46

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
AlexLanzano merged 1 commit into from
Jun 4, 2026
Merged

[stm32n6, stm32h5, eth] Change eth driver to allow the MDIO clock div to be configurable #46

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions boards/stm32h563zi_nucleo/board.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,7 @@ extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE];
.rxBufs = ethRxBufs, \
.rxDescCount = BOARD_ETH_RX_DESC_COUNT, \
.rxBufSize = BOARD_ETH_RX_BUF_SIZE, \
.mdioCr = 4, /* HCLK 168 MHz -> MDC = 168/102 ~= 1.6 MHz */ \
.timeout = &g_whalTimeout, \
}, \
}
Expand Down
1 change: 1 addition & 0 deletions boards/stm32n657a0_nucleo/board.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -315,6 +315,7 @@ extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE];
.rxBufs = ethRxBufs, \
.rxDescCount = BOARD_ETH_RX_DESC_COUNT, \
.rxBufSize = BOARD_ETH_RX_BUF_SIZE, \
.mdioCr = 0, /* HCLK 64 MHz -> MDC = 64/42 ~= 1.5 MHz */ \
.timeout = &g_whalTimeout, \
}, \
}
Expand Down
12 changes: 2 additions & 10 deletions src/eth/stm32h5_eth.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -152,14 +152,6 @@ static struct {
/* Max TX frame size */
#define ETH_MAX_FRAME_SIZE 1536

/* MDIO clock range select (CR field in MACMDIOAR). The MAC uses this to
* pick the AHB->MDC divider. Values map to AHB freq bands:
* CR=0: 60-100 MHz CR=1: 100-150 MHz
* CR=2: 20-35 MHz CR=3: 35-60 MHz
* CR=4: 150-250MHz CR=5: 250-300 MHz
* HSI default (32 MHz HCLK) -> CR=2. */
#define ETH_MDIO_CR 2

#ifdef WHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING
#define whal_Stm32h5_Eth_Init whal_Eth_Init
#define whal_Stm32h5_Eth_Deinit whal_Eth_Deinit
Expand Down Expand Up @@ -447,7 +439,7 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr,
whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos,
reg) |
whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos,
ETH_MDIO_CR) |
cfg->mdioCr) |
whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos,
ETH_MDIO_GOC_READ) |
ETH_MACMDIOAR_MB_Msk);
Expand Down Expand Up @@ -483,7 +475,7 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr,
whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos,
reg) |
whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos,
ETH_MDIO_CR) |
cfg->mdioCr) |
whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos,
ETH_MDIO_GOC_WRITE) |
ETH_MACMDIOAR_MB_Msk);
Expand Down
7 changes: 2 additions & 5 deletions src/eth/stm32n6_eth.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -161,9 +161,6 @@ static struct {
/* Default burst length */
#define ETH_PBL 32

/* MDIO clock range for AXI bus */
#define ETH_MDIO_CR 4

#ifdef WHAL_CFG_STM32N6_ETH_DIRECT_API_MAPPING
#define whal_Stm32n6_Eth_Init whal_Eth_Init
#define whal_Stm32n6_Eth_Deinit whal_Eth_Deinit
Expand Down Expand Up @@ -487,7 +484,7 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr,
whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos,
reg) |
whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos,
ETH_MDIO_CR) |
cfg->mdioCr) |
whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos,
ETH_MDIO_GOC_READ) |
ETH_MACMDIOAR_MB_Msk);
Expand Down Expand Up @@ -523,7 +520,7 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr,
whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos,
reg) |
whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos,
ETH_MDIO_CR) |
cfg->mdioCr) |
whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos,
ETH_MDIO_GOC_WRITE) |
ETH_MACMDIOAR_MB_Msk);
Expand Down
6 changes: 6 additions & 0 deletions wolfHAL/eth/stm32h5_eth.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,12 @@ typedef struct whal_Stm32h5_Eth_Cfg {
uint8_t *rxBufs; /* RX frame buffers (pre-allocated) */
size_t rxDescCount; /* Number of RX descriptors */
size_t rxBufSize; /* Size of each RX buffer in bytes */
/* MDIO clock range select (CR field in MACMDIOAR). Picks the AHB->MDC
* divider for the board's HCLK; MDC must stay <= 2.5 MHz (IEEE 802.3).
* 0: 60-100 MHz (/42) 1: 100-150 MHz (/62)
* 2: 20-35 MHz (/16) 3: 35-60 MHz (/26)
* 4: 150-250MHz (/102) 5: 250-300 MHz (/124) */
uint8_t mdioCr;
whal_Timeout *timeout;
} whal_Stm32h5_Eth_Cfg;

Expand Down
6 changes: 6 additions & 0 deletions wolfHAL/eth/stm32n6_eth.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,12 @@ typedef struct whal_Stm32n6_Eth_Cfg {
uint8_t *rxBufs; /**< RX frame buffers */
size_t rxDescCount; /**< Number of RX descriptors */
size_t rxBufSize; /**< Size of each RX buffer in bytes */
/* MDIO clock range select (CR field in MACMDIOAR). Picks the AXI->MDC
Comment thread
AlexLanzano marked this conversation as resolved.
* divider for the board's HCLK; MDC must stay <= 2.5 MHz (IEEE 802.3).
* 0: 60-100 MHz (/42) 1: 100-150 MHz (/62)
* 2: 20-35 MHz (/16) 3: 35-60 MHz (/26)
* 4: 150-250MHz (/102) 5: 250-300 MHz (/124) */
uint8_t mdioCr;
whal_Timeout *timeout;
} whal_Stm32n6_Eth_Cfg;

Expand Down
Loading