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Commit fea77e9

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Merge branch 'pci/ctrl/exynos'
- Move samsung phy-exynos-pcie init all to exynos5433_pcie_phy_init() instead of splitting across phy_init() and phy_power_on() (Marek Szyprowski) - Call phy_init() before phy_power_on() for samsung phy-exynos-pcie, as required by the PHY programming model (Marek Szyprowski) * pci/ctrl/exynos: PCI: exynos: Correct generic PHY usage phy: samsung: phy-exynos-pcie: sanitize init/power_on callbacks
2 parents 94d1331 + 22f3571 commit fea77e9

2 files changed

Lines changed: 10 additions & 18 deletions

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drivers/pci/controller/dwc/pci-exynos.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,9 +258,8 @@ static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
258258

259259
exynos_pcie_assert_core_reset(ep);
260260

261-
phy_reset(ep->phy);
262-
phy_power_on(ep->phy);
263261
phy_init(ep->phy);
262+
phy_power_on(ep->phy);
264263

265264
exynos_pcie_deassert_core_reset(ep);
266265
exynos_pcie_enable_irq_pulse(ep);

drivers/phy/samsung/phy-exynos-pcie.c

Lines changed: 9 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,13 @@ static int exynos5433_pcie_phy_init(struct phy *phy)
5151
{
5252
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
5353

54+
regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
55+
BIT(0), 1);
56+
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
57+
PCIE_APP_REQ_EXIT_L1_MODE, 0);
58+
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
59+
PCIE_REFCLK_GATING_EN, 0);
60+
5461
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
5562
PCIE_PHY_RESET, 1);
5663
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
@@ -109,20 +116,7 @@ static int exynos5433_pcie_phy_init(struct phy *phy)
109116
return 0;
110117
}
111118

112-
static int exynos5433_pcie_phy_power_on(struct phy *phy)
113-
{
114-
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
115-
116-
regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
117-
BIT(0), 1);
118-
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
119-
PCIE_APP_REQ_EXIT_L1_MODE, 0);
120-
regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
121-
PCIE_REFCLK_GATING_EN, 0);
122-
return 0;
123-
}
124-
125-
static int exynos5433_pcie_phy_power_off(struct phy *phy)
119+
static int exynos5433_pcie_phy_exit(struct phy *phy)
126120
{
127121
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
128122

@@ -135,8 +129,7 @@ static int exynos5433_pcie_phy_power_off(struct phy *phy)
135129

136130
static const struct phy_ops exynos5433_phy_ops = {
137131
.init = exynos5433_pcie_phy_init,
138-
.power_on = exynos5433_pcie_phy_power_on,
139-
.power_off = exynos5433_pcie_phy_power_off,
132+
.exit = exynos5433_pcie_phy_exit,
140133
.owner = THIS_MODULE,
141134
};
142135

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