arch/arm/stm32h5: Add USART wake from low power

Documentation/platforms/arm/stm32h5/index.rst

@@ -135,6 +135,26 @@ of the block size and count when partitioning the OTP area for their needs.
 ``len`` is the number of bytes - not words. It has no alignment requirement. ``offset`` is
 the offset in bytes. It must be a multiple of 4.
 
+Clocks
+------
+
+``STM32_BOARD_HSIKERON_ENABLE`` can be defined in board.h to keep HSI running in
+STOP mode. This can be used to keep a peripheral clocked by HSI running in
+STOP mode.
+
+``STM32_RCC_CCIPR1_U[S]ARTxSEL`` (e.g. ``STM32_RCC_CCIPR1_USART3SEL``) can be defined as one of
+
+- ``RCC_CCIPR1_U[S]ARTxSEL_RCCPCLK1``
+- ``RCC_CCIPR1_U[S]ARTxSEL_PLL2QCK``
+- ``RCC_CCIPR1_U[S]ARTxSEL_PLL3QCK``
+- ``RCC_CCIPR1_U[S]ARTxSEL_HSIKERCK``
+- ``RCC_CCIPR1_U[S]ARTxSEL_CSIKERCK``
+- ``RCC_CCIPR1_U[S]ARTxSEL_LSECK``
+
+E.g. ``RCC_CCIPR1_USART3SEL_HSIKERCK`` in board.h to select the clock source for that USART.
+The clock source is set in RCC initialization. Only stm32_serial.c is aware of this setting.
+TODO: Make stm32_lowputc.c aware of this clock source setting too.
+
 References
 =================
 [RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs

arch/arm/src/common/stm32/Kconfig.have

@@ -1069,6 +1069,9 @@ config STM32_HAVE_USART_H5
 config STM32_HAVE_USART_RXFIFO_THRESHOLD
 	bool
 
+config STM32_HAVE_USART_WUS
+	bool
+
 config STM32_HAVE_USART_UNCONFIG_ON_CLOSE
 	bool
 	default y if ARCH_CHIP_STM32H5

arch/arm/src/common/stm32/Kconfig.uart

@@ -1227,6 +1227,286 @@ config UART8_RXFIFO_THRES
 
 endif # STM32_UART8
 
+config USART1_WAKE_FROM_LOW_POWER
+	bool "USART1 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS && STM32_USART && STM32_USART1_SERIALDRIVER
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART1_WUS
+	int "USART1 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART1_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+config USART2_WAKE_FROM_LOW_POWER
+	bool "USART2 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS && STM32_USART && STM32_USART2_SERIALDRIVER
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART2_WUS
+	int "USART2 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART2_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+if STM32_USART3
+
+config USART3_WAKE_FROM_LOW_POWER
+	bool "USART3 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART3_WUS
+	int "USART3 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART3_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_USART3
+
+if STM32_UART4
+
+config UART4_WAKE_FROM_LOW_POWER
+	bool "UART4 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART4_WUS
+	int "UART4 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART4_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART4
+
+if STM32_UART5
+
+config UART5_WAKE_FROM_LOW_POWER
+	bool "UART5 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART5_WUS
+	int "UART5 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART5_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART5
+
+if STM32_USART6
+
+config USART6_WAKE_FROM_LOW_POWER
+	bool "USART6 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART6_WUS
+	int "USART6 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART6_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_USART6
+
+if STM32_UART7
+
+config UART7_WAKE_FROM_LOW_POWER
+	bool "UART7 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART7_WUS
+	int "UART7 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART7_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART7
+
+if STM32_UART8
+
+config UART8_WAKE_FROM_LOW_POWER
+	bool "UART8 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART8_WUS
+	int "UART8 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART8_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART8
+
+if STM32_UART9
+
+config UART9_WAKE_FROM_LOW_POWER
+	bool "UART9 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART9_WUS
+	int "UART9 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART9_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART9
+
+if STM32_USART10
+
+config USART10_WAKE_FROM_LOW_POWER
+	bool "USART10 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART10_WUS
+	int "USART10 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART10_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_USART10
+
+if STM32_USART11
+
+config USART11_WAKE_FROM_LOW_POWER
+	bool "USART11 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config USART11_WUS
+	int "USART11 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on USART11_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_USART11
+
+if STM32_UART12
+
+config UART12_WAKE_FROM_LOW_POWER
+	bool "UART12 Enable wake from low power mode"
+	default n
+	depends on STM32_HAVE_USART_WUS
+	---help---
+		Enable the wake from low power mode interrupt.
+		NOTE: The UART must be clocked from a clock source which is not disabled during stop
+		for this to work
+
+config UART12_WUS
+	int "UART12 Wake from low power interrupt selection"
+	default 2
+	range 0 3
+	depends on UART12_WAKE_FROM_LOW_POWER
+	---help---
+		0 = WUF active on address match (as defined by ADD[7:0] and ADDM7)
+		1 = Reserved.
+		2 = WUF active on start bit detection
+		3 = WUF active on RXNE/RXFNE.
+
+endif # STM32_UART12
+
 config STM32_USART_INVERT
 	bool "Signal Invert Support"
 	depends on STM32_USART

arch/arm/src/stm32h5/Kconfig

@@ -29,6 +29,7 @@ config STM32_H5_PERIPHERALS
 	select STM32_HAVE_USBDRD_HOST
 	select STM32_HAVE_ADC_H5
 	select STM32_HAVE_USART_H5
+	select STM32_HAVE_USART_WUS
 	select STM32_HAVE_I2C_H5
 	select STM32_HAVE_CRC
 	select STM32_HAVE_IP_WDG_M3M4_V1

arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h

@@ -65,10 +65,6 @@
 #define STM32_SYSMEM_FSIZE   0x08FFF80C     /* Size of Flash memory in Kbytes. */
 #define STM32_SYSMEM_PACKAGE 0x08FFF80E     /* Indicates the device's package type. */
 
-/* OTP Base Addresses *******************************************************/
-
-#define STM32_OTP_BASE       0x08fff000     /* Base address of OTP Area */
-
 /* Peripheral Base Addresses ************************************************/
 
 #define STM32_APB1_BASE      0x40000000     /* 0x40000000-0x4000fbff: APB1 */

arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h

@@ -823,7 +823,7 @@
 
 #define RCC_CCIPR1_USART1SEL_SHIFT        (0)
 #define RCC_CCIPR1_USART1SEL_MASK         (7 << RCC_CCIPR1_USART1SEL_SHIFT)
-#  define RCC_CCIPR1_USART1SEL_RCCPCLK1   (0 << RCC_CCIPR1_USART1SEL_SHIFT)
+#  define RCC_CCIPR1_USART1SEL_RCCPCLK2   (0 << RCC_CCIPR1_USART1SEL_SHIFT)
 #  define RCC_CCIPR1_USART1SEL_PLL2QCK    (1 << RCC_CCIPR1_USART1SEL_SHIFT)
 #  define RCC_CCIPR1_USART1SEL_PLL3QCK    (2 << RCC_CCIPR1_USART1SEL_SHIFT)
 #  define RCC_CCIPR1_USART1SEL_HSIKERCK   (3 << RCC_CCIPR1_USART1SEL_SHIFT)
@@ -866,14 +866,14 @@
 #  define RCC_CCIPR1_UART5SEL_CSIKERCK   (4 << RCC_CCIPR1_UART5SEL_SHIFT)
 #  define RCC_CCIPR1_UART5SEL_LSECK      (5 << RCC_CCIPR1_UART5SEL_SHIFT)
 
-#define RCC_CCIPR1_UART6SEL_SHIFT        (15)
-#define RCC_CCIPR1_UART6SEL_MASK         (7 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_RCCPCLK1   (0 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_PLL2QCK    (1 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_PLL3QCK    (2 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_HSIKERCK   (3 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_CSIKERCK   (4 << RCC_CCIPR1_UART6SEL_SHIFT)
-#  define RCC_CCIPR1_UART6SEL_LSECK      (5 << RCC_CCIPR1_UART6SEL_SHIFT)
+#define RCC_CCIPR1_USART6SEL_SHIFT       (15)
+#define RCC_CCIPR1_USART6SEL_MASK        (7 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_RCCPCLK1  (0 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_PLL2QCK   (1 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_PLL3QCK   (2 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_HSIKERCK  (3 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_CSIKERCK  (4 << RCC_CCIPR1_USART6SEL_SHIFT)
+#  define RCC_CCIPR1_USART6SEL_LSECK     (5 << RCC_CCIPR1_USART6SEL_SHIFT)
 
 #define RCC_CCIPR1_UART7SEL_SHIFT        (18)
 #define RCC_CCIPR1_UART7SEL_MASK         (7 << RCC_CCIPR1_UART7SEL_SHIFT)
@@ -924,14 +924,14 @@
 #  define RCC_CCIPR2_USART11SEL_CSIKERCK   (4 << RCC_CCIPR2_USART11SEL_SHIFT)
 #  define RCC_CCIPR2_USART11SEL_LSECK      (5 << RCC_CCIPR2_USART11SEL_SHIFT)
 
-#define RCC_CCIPR2_USART12SEL_SHIFT        (4)
-#define RCC_CCIPR2_USART12SEL_MASK         (7 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_RCCPCLK1   (0 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_PLL2QCK    (1 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_PLL3QCK    (2 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_HSIKERCK   (3 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_CSIKERCK   (4 << RCC_CCIPR2_USART12SEL_SHIFT)
-#  define RCC_CCIPR2_USART12SEL_LSECK      (5 << RCC_CCIPR2_USART12SEL_SHIFT)
+#define RCC_CCIPR2_UART12SEL_SHIFT         (4)
+#define RCC_CCIPR2_UART12SEL_MASK          (7 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_RCCPCLK1    (0 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_PLL2QCK     (1 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_PLL3QCK     (2 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_HSIKERCK    (3 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_CSIKERCK    (4 << RCC_CCIPR2_UART12SEL_SHIFT)
+#  define RCC_CCIPR2_UART12SEL_LSECK       (5 << RCC_CCIPR2_UART12SEL_SHIFT)
 
 #define RCC_CCIPR2_LPTIM1SEL_SHIFT         (8)
 #define RCC_CCIPR2_LPTIM1SEL_MASK          (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT)