[Sim] Implement the lowering logic from sim.proc.print to the SV dialect by nanjo712 · Pull Request #10172 · llvm/circt

nanjo712 · 2026-04-10T10:31:01Z

This PR lowers sim.proc.print to SystemVerilog sv.fwrite.

It only handles the procedural form of print operations. Non-procedural sim.print is expected to be converted first, for example by --sim-proceduralize.

This PR does not add stream support yet.

Split from #10146 .

AI-assisted-by: OpenAI ChatGPT

nanjo712 · 2026-04-10T11:23:22Z

lib/Conversion/SimToSV/SimToSV.cpp

+      return failure();
+    }
+
+    // Align with FIRRTLToHW: default to writing to stderr.


I'm not entirely sure if this is the right approach. The current purpose is to ensure that the observable behavior remains consistent if the full lowering path FIRRTL->Sim->SV is added in the future.

I'd prefer to lower to $write instead of $fwrite if no stream is specified. We can then restore the FIRRTL behavior by adding a sim.stderr_stream operation.

I think that sounds like a good direction. However, the current SV dialect does not seem to have an operation corresponding to $write.

For this PR, I'd prefer to preserve the existing behavior and keep lowering streamless prints to the same default error stream as the current FIRRTL-to-SV path.

Would it be okay to refine this in a follow-up PR once we have explicit support for $write on the SV side?

I re-examined sv.fwrite, and we can simulate the behavior of $write by specifying that it outputs to stdout. I'm not entirely sure if adding an sv.write just to represent $write is worthwhile, since $fwrite already covers this capability.

I've implemented sv.write in #10179.

fzi-hielscher

It is generally not recommended to traverse def-use-chains within the dialect conversion framework, so an OpConversionPattern is not ideal for lowering the print operations. We should perform the lowering of sim.proc.print before doing the dialect conversion. I would suggest to:

Find and convert the print operations
Run Region DCE on the bodies of the affected hw.triggered ops to remove the dangling formatting ops.
Run the dialect conversion

lib/Conversion/SimToSV/SimToSV.cpp

nanjo712 · 2026-04-10T15:38:49Z

lib/Conversion/SimToSV/LowerPrintFormattedProcToSV.cpp

+  return success();
+}
+
+static Operation *findProceduralRoot(Operation *op) {


After using proceduralize-sim, we need to lower hw.triggered to the sv dialect before we can lower sim.proc.print to sv.fwrite; otherwise, the constraints of sv.fwrite cannot be satisfied. This is why I haven't added hw.triggered to the whitelist here.

nanjo712 · 2026-04-10T15:40:33Z

test/Conversion/SimToSV/lower-print-formatted-proc-to-sv-errors.mlir

+
+// -----
+
+hw.module @unsupported_procedural_root(in %clk : i1) {


The hw.triggered should be lower to SV dialect first as sv.fwrite is only allowed to appear in the procedure block of sv.

fabianschuiki

Really amazing effort @nanjo712 🥳, thanks for pushing this forward! One thing I noticed: you had this neatly tucked into the SimToSV conversion earlier, which feels like the right spot to convert a sim.proc.print op to sv.fwrite. Would it make sense to go back to that? That would eventually allow us to have SimTransforms not link against the SV dialect anymore -- all the patterns that touch both Sim and SV would live in the SimToSV conversion. WDYT?

nanjo712 · 2026-04-10T17:04:15Z

Really amazing effort @nanjo712 🥳, thanks for pushing this forward! One thing I noticed: you had this neatly tucked into the SimToSV conversion earlier, which feels like the right spot to convert a sim.proc.print op to sv.fwrite. Would it make sense to go back to that? That would eventually allow us to have SimTransforms not link against the SV dialect anymore -- all the patterns that touch both Sim and SV would live in the SimToSV conversion. WDYT?

That sounds reasonable. I must have misunderstood some of the previous reviews, sorry.

…ect. AI-assisted-by: OpenAI ChatGPT

fzi-hielscher · 2026-04-10T17:17:23Z

The hw.triggered should be lower to SV dialect first as sv.fwrite is only allowed to appear in the procedure block of sv.

Yeah.. I now remember the problem with the SV procedural region trait : #7314 🫤
If you do the ProcPrint to FWrite conversion as part of the same pass but before applyPartialConversion does this still cause a verification error? Since I've posted that PR, LLHD has also gained its own procedural region trait. Do you think we could unify the LLHD and SV flavor in the HW dialect and add it to hw.triggered, @fabianschuiki?

fabianschuiki · 2026-04-10T19:13:40Z

It would be great to have a unified trait for that! I wonder whether this could live somewhere in CIRCTSupport or so, since it seems to be mostly orthogonal to the actual dialects. WDYT @fzi-hielscher?

uenoku · 2026-04-10T19:46:54Z

Having a common trait would be great 🙏 I encountered this a few times in the past and it was really annoying to avoid.

nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch from d2a978d to 5358f98 Compare April 10, 2026 10:54

nanjo712 marked this pull request as ready for review April 10, 2026 11:07

nanjo712 commented Apr 10, 2026

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fzi-hielscher reviewed Apr 10, 2026

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nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch 2 times, most recently from 62e153a to ee209ff Compare April 10, 2026 14:53

nanjo712 changed the title ~~[SimToSV] Implement sim.proc.print lowering logic~~ [Sim] Implement the lowering logic from sim.proc.print to the SV dialect Apr 10, 2026

nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch 3 times, most recently from 19f96ea to 4e6adb2 Compare April 10, 2026 15:34

nanjo712 commented Apr 10, 2026

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nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch 2 times, most recently from 672d519 to 3911e4b Compare April 10, 2026 15:45

nanjo712 requested a review from fzi-hielscher April 10, 2026 15:57

fabianschuiki reviewed Apr 10, 2026

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nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch 2 times, most recently from 91262c9 to e314a09 Compare April 10, 2026 17:02

[Sim] Implement the lowering logic from sim.proc.print to the SV dial…

d0dae92

…ect. AI-assisted-by: OpenAI ChatGPT

nanjo712 force-pushed the feat/lower-sim-proc-print-to-sv branch from e314a09 to d0dae92 Compare April 10, 2026 17:17

nanjo712 mentioned this pull request Apr 11, 2026

[SV][ExportVerilog] Add sv.write for no-stream writes #10179

Open


		// -----

		hw.module @unsupported_procedural_root(in %clk : i1) {

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